Processor memory element and a new computer architecture

Claim 1

A computer system for performing arithmetic and logic operations, the system comprising: a plurality of processor memory elements, each processor memory element comprising addressable combination processor and memory cells, each cell including (1) accumulator means for storing data and (2) arithmetic logic means for performing arithmetic and logic operations on the contents of the accumulator means; a plurality of parallel source bus means in communication with each cell for providing access to the accumulator means and artihmetic logic means of each cell; source bus selection means for selecting simultaneously a source cell, a destination cell, and one of the source bus means; execution means for causing the contents of the accumulator means in the source cell to be placed onto the selected source bus means, and for causing the arithmetic logic means of the destination cell to perform arithmetic and logic operations based on the contents of the selected source bus means and on the data contained in the accumulator of the destination cell; means for inputing and outputing data into and out of the execution means; and instruction means for transmitting a series of instructions to the execution means, the instruction means including means for executing branch, indexing, and subroutine instructions, and further comprising means for controlling and sequencing instruction words with multiple subwords.