US4804941A — Circuit for compensating a linearity of an input/…

Claim 1

Independent Claim 218 words

A circuit for compensating an input/output characteristic linearity of an analog-to-digital converter, comprising: (a) first means for providing a first current having a magnitude corresponding to a second current which is an amplification of an input current flowing through an input circuit of one of a plurality of comparators in the analog-to-digital converter from a chain of resistors providing each of a plurality of comparison reference voltages for the corresponding one of the comparators; (b) second means for providing a third current on the basis of the first current, the third current being a multiplication of a second current by a predetermined multiplication factor; (c) third means for providing a fourth current on the basis of the third current, the fourth current being a multiplication of the third current by an inverse of an amplification factor of the input circuit of the comparator; and (d) fourth means for providing a fifth current on the basis of the fourth current, the fifth current being a multiplication of the fourth current by a second predetermined multiplication factor and being supplied to the input circuit so as to compensate for a first input current flow totally supplied from a reference voltage supply of the resistor chain to a predetermined group of the input circuits of the comparators via the resistor chain.

Claim 2

Dependent Claim 218 words

A circuit for compensating an input/output characteristic linearity of an analog-to-digital converter, comprising: (a) first means for providing a first current having a magnitude corresponding to a second current which is an amplification of an input current flowing through an input circuit of one of a plurality of comparators in the analog-to-digital converter from a chain of resistors providing each of a plurality of comparison reference voltages for the corresponding one of the comparators; (b) second means for providing a third current on the basis of the first current, the third current being a multiplication of a second current by a predetermined multiplication factor; (c) third means for providing a fourth current on the basis of the third current, the fourth current being a multiplication of the third current by an inverse of an amplification factor of the input circuit of the comparator; and (d) fourth means for providing a fifth current on the basis of the fourth current, the fifth current being a multiplication of the fourth current by a second predetermined multiplication factor and being supplied to the input circuit so as to compensate for a first input current flow totally supplied from a reference voltage supply of the resistor chain to a predetermined group of the input circuits of the comparators via the resistor chain.

Claim 3

Dependent Claim 112 words

A circuit as set forth in claim 1, wherein the first means supplies the fifth current to the input circuit of one of the other comparators so as to compensate for a second input current flow totally supplied from the reference voltage supply to a second predetermined group of the input circuits of the comparators subsequent to the predetermined group via the resistor chain and to the input circuit of another one of the other comparators so as to compensate for a third input current flow totally supplied from the reference voltage supply to a third group of input circuits of the comparators via the resistor chain subsequent to the second group.

Claim 4

Dependent Claim 50 words

A circuit as set forth in claim 1, wherein the first means comprises a plurality of first circuits, each first circuit being a dummy bias circuit having the same construction as a bias circuit of each comparator and providing the first current having the magnitude equal to the second current.

Claim 5

Dependent Claim 31 words

A circuit as set forth in claim 3, wherein the second means comprises a plurality of first current multipliers each of which multiplies the first current by the first multiplication factor.

Claim 6

Dependent Claim 17 words

A circuit as set forth in claim 4, wherein the first multiplication factor is a positive integer.

Claim 7

Dependent Claim 24 words

A circuit as set forth in claim 4, wherein the first predetermined multiplication factor has a different value from the second predetermined multiplication factor.

Claim 8

Dependent Claim 22 words

A circuit as set forth in claim 4, wherein the first predetermined factor has the same value as the second predetermined factor.

Claim 9

Dependent Claim 33 words

A circuit as set forth in claim 4, wherein each of the first current multipliers constitutes a first current Miller circuit together with a predetermined emitter follower transistor of the corresponding first circuit.

Claim 10

Dependent Claim 31 words

A circuit as set forth in claim 4, wherein the fourth means comprises a plurality of second current multipliers each of which multiplies the fourth current by the second multiplication factor.

Claim 11

Dependent Claim 17 words

A circuit as set forth in claim 9, wherein the second multiplication factor is a positive integer.

Claim 12

Dependent Claim 44 words

A circuit as set forth in claim 9, wherein the fourth means further includes a plurality of first emitter follower transistors and wherein each of the second current multipliers constitutes a second Miller circuit together with the corresponding one of the emitter follower transistors.

Claim 13

Dependent Claim 62 words

A circuit as set forth in claim 9, wherein each of the second Miller circuits comprises a plurality of parallel emitter follower transistors whose collectors are interconnected to provide the fifth current and whose bases are interconnected to another transistor for compensating an emitter-grounded current amplification factor of the first and second emitter follower transistors of the corresponding second current Miller circuit.

Claim 14

Dependent Claim 57 words

A circuit as set forth in claim 9, wherein the third means comprises a plurality of a set of first transistors each set of the first transistors connected between the corresponding first and second circuits and having an emitter grounded current amplification factor equal to that of an input transistor of the input circuit of the comparator.

Claim 15

Dependent Claim 51 words

A circuit as set forth in claim 13, wherein the numbers of the first circuits, first current multipliers, second current multipliers, the set of the first transistors are mutually the same and are determined on the basis of the number of bits of an output digital signal of the analog-to-digital converter.

Claim 16

Dependent Claim 224 words

A circuitry for compensating an input/output characteristic linearity of an 8-bit analog-to-digital converter, comprising: (a) three first circuits, each first circuit providing a first current having a magnitude corresponding to a second current I E which is an amplification of an input current i flowing through an input circuit of one of a plurality of comparators in the 8-bit analog-to-digital converter from a resistor chain providing each of a plurality of mutually different levels of comparison reference voltages for the corresponding one of the comparators; (b) three second circuits, each second circuit providing a third current kI E on the basis of the first current, the third current kI E being a multiplicater of the second current I E by a first factor of a positive integer k; (c) three third circuits, each third circuit providing a fourth current ki on the basis of the third current kI E , the fourth current being a multiplication of the third current kI E by an inverse of an emitter-grounded current amplification factor β of the input circuit; and (d) three fourth circuits, each fourth circuit providing a fifth current kli on the basis of the fourth current, the fifth current being a multiplication of the fourth current ki by a second factor of a positive integer l and being supplied to a predetermined one of

Claim 17

Dependent Claim 224 words

A circuitry for compensating an input/output characteristic linearity of an 8-bit analog-to-digital converter, comprising: (a) three first circuits, each first circuit providing a first current having a magnitude corresponding to a second current I E which is an amplification of an input current i flowing through an input circuit of one of a plurality of comparators in the 8-bit analog-to-digital converter from a resistor chain providing each of a plurality of mutually different levels of comparison reference voltages for the corresponding one of the comparators; (b) three second circuits, each second circuit providing a third current kI E on the basis of the first current, the third current kI E being a multiplicater of the second current I E by a first factor of a positive integer k; (c) three third circuits, each third circuit providing a fourth current ki on the basis of the third current kI E , the fourth current being a multiplication of the third current kI E by an inverse of an emitter-grounded current amplification factor β of the input circuit; and (d) three fourth circuits, each fourth circuit providing a fifth current kli on the basis of the fourth current, the fifth current being a multiplication of the fourth current ki by a second factor of a positive integer l and being supplied to a predetermined one of

Claim 18

Dependent Claim 20 words

A circuitry as set forth in claim 15, wherein the first factor is 8 and the second factor is 8.

Claim 19

Dependent Claim 48 words

A circuitry as set forth in claim 16, wherein one of the three fifth currents 64i is supplied to the 64th comparator, one of the other two fifth currents 64i is suppied to the 128th comparator, and the remaining fifth current 64i is supplied to the 192nd comparator.

Claim 20

Dependent Claim 51 words

A circuitry as set forth in claim 15, wherein each of the first circuits has the same construction of a bias circuit of each comparator and includes a first emitter follower transistor and a resistor connected between the first transistor and a minus terminal of a power supply of the circuitry.

Claim 21

Dependent Claim 39 words

A circuitry as set forth in claim 18, wherein each of the second circuits comprises a first current multiplier having the first factor of multiplication and connected to the first transistor of the corresponding one of the first circuits.

Claim 22

Dependent Claim 70 words

A circuitry as set forth in claim 19, wherein the first current multiplier comprises a first current Miller circuit together with the first transistor of the first circuit, the first current Miller circuit having a plurality of parallel-connected second transistors whose bases are interconnected to the base of the first transistor and through each emitter of which the current equal to the first current I E flows via a resistor.

Claim 23

Dependent Claim 52 words

A circuitry as set forth in claim 20, wherein a value of the resistor connected between the emitter of the first transistor and a minus terminal of the power supply has the same value as each of the resistors connected between the emitter of each corresponding second transistor and the minus terminal.

Claim 24

Dependent Claim 67 words

A circuitry as set forth in claim 20, wherein each of the third circuits comprises two third transistors whose bases, emitters, and collectors are mutually connected and whose emitters are connected to the collectors of the second transistors of the first current Miller circuit so that the current expressed as kαI E (α denotes a base-grounded current amplification factor) flows into the bases of the third transistors.

Claim 25

Dependent Claim 41 words

A circuitry as set forth in claim 22, wherein each of the fourth circuits comprises a second current multiplier having the second factor of multiplication and connected to the base of the third transistors via an emitter of a fourth transistor.

Claim 26

Dependent Claim 32 words

A circuitry as set forth in claim 23, wherein the first current multiplier has the first multiplication factor of 8 and the second current multiplier has the second multiplication factor of 8.

Claim 27

Dependent Claim 32 words

A circuitry as set forth in claim 23, wherein the first current multiplier has the first multiplication factor of 4 and the second current multiplier has the second multiplication factor of 16.

Claim 28

Dependent Claim 121 words

A circuitry as set forth in claim 23, wherein the second current multiplier comprises a plurality of parallel-connected fifth transistors whose bases are mutually connected and connected to the emitter of the fourth transistor, whose emitters are respectively connected to a zero terminal of the power supply via resistors, and whose collectors are interconnected to supply the fifth current to the predetermined one of the comparators, the plurality of parallel-connected fifth transistors constituting a second current Miller circuit together with a sixth transistor whose emitter is connected to the zero terminal of the power supply via a resistor, whose base is connected to the base of each fifth transistor, and whose collector is connected to the base of the fourth transistor.

Claim 29

Dependent Claim 25 words

A circuitry as set forth in claim 26, wherein the numbers of the second and fifth transistors are varied according to the first multiplication factor.

Claim 30

Dependent Claim 219 words

A circuit for compensating an input/output characteristic linearity of an analog-to-digital converter, comprising: (a) first circuit means for providing a first current having a magnitude substantially equal to a second current I E which is an amplification of an input current i flowing through an input circuit for one of a plurality of comparators of the analog-to-digital converter from a chain of resistors providing each of mutually different levels of comparison reference voltage for the corresponding one of the comparators; (b) second circuit means for providing a third current kI E on the basis of the first current, the third current kI E being a multiplication of the second current I E by a first multiplication factor k; (c) third circuit means for providing a fourth current ki on the basis of the third current kI E , the fourth current ki being a multiplication of the third current by an inverse of an amplification factor of an input transistor in the input circuit for the corresponding comparison voltage of the input circuit; and (d) fourth circuit means for providing a fifth current kli on the basis of the fourth current ki, the fifth current being a multiplication of the fourth current ki by a second multiplication factor l and being supplied to a predetermined one of the comparators.

Claim 31

Dependent Claim 219 words

A circuit for compensating an input/output characteristic linearity of an analog-to-digital converter, comprising: (a) first circuit means for providing a first current having a magnitude substantially equal to a second current I E which is an amplification of an input current i flowing through an input circuit for one of a plurality of comparators of the analog-to-digital converter from a chain of resistors providing each of mutually different levels of comparison reference voltage for the corresponding one of the comparators; (b) second circuit means for providing a third current kI E on the basis of the first current, the third current kI E being a multiplication of the second current I E by a first multiplication factor k; (c) third circuit means for providing a fourth current ki on the basis of the third current kI E , the fourth current ki being a multiplication of the third current by an inverse of an amplification factor of an input transistor in the input circuit for the corresponding comparison voltage of the input circuit; and (d) fourth circuit means for providing a fifth current kli on the basis of the fourth current ki, the fifth current being a multiplication of the fourth current ki by a second multiplication factor l and being supplied to a predetermined one of the comparators.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1992-02-14	1992-08-15	1993-02-14	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1996-02-14	1996-08-15	1997-02-14	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2000-02-14	2000-08-15	2001-02-14	$7700.00	Window Closed / Lapsed

Circuit for compensating a linearity of an input/output characteristic of a parallel comparison type analog-to-digital converter

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