US4803178A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making silicon-on-sapphire gate array
Assignee: PLESSY SEMICONDUCTORS Ltd
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Filing: 1987-11-30
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Granted: 1989-02-07
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Expires: 2007-11-30
Abstract
Abstract A semiconductor arrangement has a substrate which carries a partially filled array of semiconductor cells, and utilises the vacant sites in the array to position interconnecting tracks. A filled array is manufactured, and when the electrical function of the arrangement has been allocated, those semiconductor cells, each of which contains active semiconductor devices, which are not needed to perform the allocated function are removed. The vacant sites so formed are then occupied by electrically conductive tracks. The arrangement is suitable for silicon-on-sapphire gate arrays.
Inventors
- 👤 Daniel V. McCaughan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:28
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/641; Y; Y10; Y10S; Y10S148/00; Y10S148/15
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
65 words
A method of making a semiconductor arrangement including the steps of forming a closely packed regular array of semiconductor island cells, each cell of which includes a semiconductor device and is formed on an insulating substrate; removing selected cells to leave a partially filled array; and forming electrically conductive interconnections for remaining cells, the interconnections at least partly overlying the sites of the removed cells.
Claim 2
Independent Claim
65 words
A method of making a semiconductor arrangement including the steps of forming a closely packed regular array of semiconductor island cells, each cell of which includes a semiconductor device and is formed on an insulating substrate; removing selected cells to leave a partially filled array; and forming electrically conductive interconnections for remaining cells, the interconnections at least partly overlying the sites of the removed cells.
Claim 3
Dependent Claim
22 words
A method as claimed in claim 1 and wherein the selected cells are removed to expose the surface of the insulating substrate.
Claim 4
Dependent Claim
34 words
A method as claimed in claim 3 and wherein said electrically conductive interconnections take the form of metallic tracks in contact with the surface of said substrate to constitute a first layer of interconnection.
Claim 5
Dependent Claim
35 words
A method as claimed in claim 3 and wherein a second layer of interconnection is produced by forming another layer of metallic tracks on an electrically insulating layer which overlies said first layer of interconnection.
Claim 6
Dependent Claim
36 words
A method as claimed in claim 2 and wherein following the formation of the closely packed regular array of semiconductor island cells, the cells are coated with a passivating layer of an inert electrically insulating material.
Claim 7
Dependent Claim
44 words
A method as claimed in claim 5 and following the allocation of a circuit function to said arrangement, and the removal of said selected cells, apertures are opened in said passivating lyer to permit electrical connection between remaining cells and the electrically conductive interconnections.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-07 | 1992-08-08 | 1993-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-07 | 1996-08-08 | 1997-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-07 | 2000-08-08 | 2001-02-07 | $7700.00 | Window Closed / Lapsed |