Data monitor apparatus

Claim 2

A data monitor apparatus comprising: (a) reference data generator circuit means for generating reference data representing normal received data; (b) comparator circuit means for comparing actual received data with said reference data from said reference data generator circuit means, said comparator circuit means producing a signal when it detects a segment of the actual received data which deviates from said normal received data; (c) recorder circuit means for recording an output from said comparator circuit means; (d) a compressed data recorder circuit; and (e) pointer control circuit means cooperable with said compressed data recorder circuit and responsive to the occurrence of said signal from said comparator circuit means for causing said compressed data recorder circuit to store a portion of said actual received data which includes said segment thereof.

Claim 3

A data monitor apparatus according to claim 1, wherein said compressed data recorder circuit includes memory means for storing data, and wherein said pointer control circuit means includes: (a) a first counter having said signal from said comparator circuit means as an input; (b) first setting unit means for providing a remaining count value to said first counter, said first counter accepting said remaining count value in response to said signal from said comparator circuit means; (c) a second counter having said signal from said comparator circuit means as an input; (d) second setting unit means for providing a remaining count value to said second counter, said second counter accepting said remaining count value in response to said signal from said comparator circuit means; (e) a selector having said actual received data as an input and having first and second outputs, said selector supplying said actual received data from its input to a selected one of its first and second outputs in dependence on output signals from said first and second counters; (f) a first pointer circuit coupled to said compressed data recorder circuit and having said first output from said selector as an input, said first pointer circuit transmitting data from said first output of said selector to said memory means of said compressed data recorder circuit and specifying where in said memory means such data is to be stored; and (g) a second pointer circuit coupled to said compressed data recorder circuit and having said second output from said selector as an input, said second pointer circuit transmitting data from said second output of said selector to said memory means of said compressed data recorder circuit and specifying where in said memory means such data is to be stored.

Claim 4

A data monitor apparatus according to claim 2, wherein said compressed data recorder circuit includes: (a) first recorder circuit means for recording said received data from said first pointer circuit, said first recorder circuit means including a first portion of said memory means; and (b) second recorder circuit means for recording said received data from said second pointer circuit, said second recorder circuit means including a second portion of said memory means.

Claim 5

A data monitor apparatus according to claim 2, wherein said first counter counts units of received data stored in said memory means by said first pointer circuit and produces said output signal thereof when, after accepting the remaining count value provided to it, it has counted a number of units of data equal to such remaining count value, wherein said second counter counts units of received data stored in said memory means by said second pointer circuit and produces said output signal thereof when, after accepting the remaining count value provided to it, it has counted a number of units of data equal to such remaining count value, and wherein said selector respectively selects its first and second outputs in response to said output signals from said second and first counters, respectively.

Claim 6

A data monitor apparatus according to claim 4, wherein each said portion of said actual received data stored in said memory means is n successive bytes thereof which immediately precede the output signal from one of said first and second counters; and wherein the remaining count value provided to said one of said counters is n-x when x<n/2, and is n/2 when x>n/2, where x is the number of bytes of actual received data which were received between an immediately preceding output signal from the other of said counters and the next said signal thereafter produced by said comparator circuit means.