Semiconductor integrated circuit device

Claim 2

An IC memory device comprising: an address decoder for selecting a memory cell of said memory device; a bit line for reading information out from a selected memory cell, said selected memory cell including a storage capacitor and a plurality of FETs, one FET of said plurality of FETs connecting said storage capacitor to said bit line, said FET having a back-gate electrode for controlling a threshold voltage of said FET, a gate electrode connected to an output of said address decoder, a first switched electrode connected to said bit line and a second switched electrode connected to said storage capacitor and a voltage source circuit which supplies said backgate electrode of said FET with a prescribed voltage for raising the threshold voltage of said FET of said memory cell above threshold voltages of the remaining FET(s) of said plurality of FETs to reduce a charge leakage from said storage capacitor.

Claim 3

An IC device in accordance with claim 1, wherein said remaining FET(s) also has a back-gate electrode(s).

Claim 4

An IC memory device comprising: a voltage source circuit; a memory cell for storing information; a bit line for reading information out from said memory cell; an address decoder for selecting said memory cell in response to an address signal; and a word line for connecting an output of said memory cell to said bit line, said memory cell including a storage capacitor, a first FET for gating an output of said address decoder onto said word line, said first FET having a first threshold voltage and including a gate electrode connected to an output of said address decoder, a first switched electrode connected to a source of a control signal, and a second switched electrode connected to said word line, and a second FET connecting said storage capacitor to said bit line, said second FET having a back-gate electrode for controlling a threshold of said second FET, a gate electrode connected to an output of said address decoder, a first switched electrode connected to said bit line and a second switched electrode connected to said storage capacitor, wherein said voltage source circuit supplies said back-gate electrode of said second FET with a prescribed voltage for raising said second threshold voltage of said second FET of said memory cell above that of said threshold voltages of said first FET to reduce a charge leakage from said storage capacitor.

Claim 5

An IC memory device comprising: a voltage source circuit; a memory cell for storing information; a bit line for reading information out from said memory cell; an address decoder for selecting said memory cell in response to an address signal; and a word line for connecting an output of said memory cell to said bit line, said memory cell including a storage capacitor, a first FET for gating an output of said address decoder onto said word line, said first FET having a first threshold voltage and including a gate electrode connected to an output of said address decoder, a first switched electrode connected to a source of a control signal, and a second switched electrode connected to said word line, and a second FET connecting said storage capacitor to said bit line, said second FET having a back-gate electrode for controlling a threshold of said second FET, a gate electrode connected to an output of said address decoder, a first switched electrode connected to said bit line and a second switched electrode connected to said storage capacitor, wherein said voltage source circuit supplies said back-gate electrode of said second FET with a prescribed voltage for raising said second threshold voltage of said second FET of said memory cell above that of said threshold voltages of said first FET to reduce a charge leakage from said storage capacitor.

Claim 6

An IC memory device in accordance with Claim 3 wherein said voltage source comprises: a control signal input terminal for receiving a control signal; a voltage supply input terminal for receiving a source of input voltage; an output node for supplying said prescribed voltage to said back-gate electrode of said second FET; a discharge FET having a gate electrode and a first switched electrode both connected to said control signal input terminal for receiving a control signal, a second switched electrode connected to said voltage supply input terminal, and a back-gate electrode for controlling a threshold of said discharge FET connected to said output node; a rectification FET having gate, first switched, and back-gate electrodes connected to said output node, and a second switched electrode connected to said control signal input terminal.