Speed reducing signal

Claim 2

A speed reduction signaling apparatus for use in an automotive vehicle having an electrical power system and a rotatable mechanical system comprising: a speed responsive pickup system cooperative with a plurality of permanent magnets mounted on said rotatable mechanical system and which emits pulses at a rate responsive to said vehicle's speed; a timing circuit means for independently providing clock timing pulses at a predetermined rate and establishing speed threshold; logic circuitry means cooperative with said speed responsive pickup system and said timing circuit means for determining when said vehicle's speed has fallen below said speed threshold; a plurality of external lamp means cooperative with said logic circuitry means and which are caused to alternately flash on and off by said logic circuitry means whenever the rate of said pulses which are emitted by said speed responsive pickup system falls below said speed threshold; and electrical connections for receiving electrical energy for said speed responsive pickup system, said timing circuit means, said logic circuitry means, and said external lamp means and adapted for connection to said electrical power system.

Claim 3

The apparatus as claimed in claim 1 wherein the timing circuit means includes: a counter means having a clock pulse input for receiving timing pulses, a reset input, and a plurality of outputs; a variable oscillator means for emitting periodic electrical pulses at a predetermined rate to establish a speed threshold, and having an output coupled to said clock pulse input of said counter means and to a plurality of inputs in the said logic circuitry means; and oscillator adjustment means for varying the frequency of oscillator output.

Claim 4

The apparatus as claimed in claim 2 wherein the logic circuitry means further comprises: a speed threshold detector means for determining when the speed of the vehicle has dropped below a speed threshold value; a reset trigger means having a plurality of inputs and a single output coupled to the reset input of said counter means and the reset input of said speed threshold detector means; divider circuitry means for causing said plurality of external lamp means to flash alternately on and off; sampling means coupled to the output of the speed responsive pickup system and providing input signals to the divider circuitry means and speed threshold detector means; first switch means for connecting said divider circuitry means to a first output of the counter means to cause the plurality of external lamp means to alternately flash on and off at a fixed rate, or to said speed responsive pickup system to cause the plurality of external lamp means to flash on and off at a variable rate; and second switch means for connecting a second output of the counter means to one of said external lamp means whenever the output of said speed threshold detector means drops below a speed threshold value corresponding essentially to a full stop to keep said external lamp means on steadily.

Claim 5

The apparatus as claimed in claim 3 wherein the external lamp means includes: amplifier means having a first input conncted to an output from the divider circuitry means, and a second input connected to an output from the speed threshold detector means, and an output; first transistor means having a base electrode input connected to the output of said amplifier means, and an output; second transistor means having a base electrode input connected to the output of said first transistor means, and an output; a lamp for external warning which is illuminated by output from said second transistor means; and a light emitting diode for operator display which is activated by output from said second transistor means.

Claim 6

The apparatus as claimed in claim 4 wherein the speed responsive pickup system further comprises: a reluctance pickup coil having two ends for producing an output pulse in response to a magnetic flux field caused by said permanent magnets; a first amplifier means having inverting and non-inverting inputs connected to opposite ends of said reluctance pick-up coil for producing a speed responsive output pulse; a second amplifier means having a non-inverting input connected to the output of said first amplifier means, and having an inverting input connected to the output for producing a delayed output signal; and a flip-flop having a clock input connected to the output of said second amplifier means, and an output for enabling the sampling means.

Claim 7

The apparatus as claimed in claim 5 wherein the sampling means includes combinational logic gates coupled to the speed responsive pickup system, and to the divider circuitry means and the speed threshold detector means, for producing an output pulse when enabled by the speed responsive pickup system.