System incorporating an error tolerant picture compression algorithm

Claim 3

The method of claim 1 and further comprising the steps of: I. transmitting said encoded, quantized signals, and said generated bitmaps to a decoder; II. decoding said encoded, quantized signals, and said generated bitmaps; and III. decompressing said decoded quantized signals, and said generated bitmaps to form reconstructed Y, I and Q image plane signals.

Claim 4

The method according to claim 1 wherein the signal processing for the Y, I and Q plane image signals is performed in parallel.

Claim 7

The system according to claim 4 wherein said input buffer means is comprised of: a pair of memory banks for each of said Y, I and Q signals; an input switching means for toggling between said pair of memory banks to fill first one bank and then the other; an output switching means for toggling between said pair of memory banks to empty filled memory banks; and an address generator means coupled to said memory banks for addressing the locations in said memory banks for storing said Y, I and Q signals in block format.

Claim 8

The system according to claim 5 wherein said address generator means is comprised of: a counter having an input for receiving a system clock signal and having multiple outputs corresponding in number to the number of binary bits forming the Y, I or Q signal on which outputs the bits corresponding to the count in the counter appear; and memory addressing means responsive to the bit count on the multiple outputs of said counter for addressing said pair of memory banks so as to fill said memory banks in a block format.

Claim 9

The system according to claim 6 wherein said counter is a 12-bit counter having outputs A 0 -A 11 ; and wherein said memory addressing means has address inputs A 0 -A 11 and wherein the outputs of said counter are connected to the address inputs of said memory addressing means as follows: ______________________________________ counter means memory addressing means ______________________________________ A.sub.0 A.sub.0 A.sub.1 A.sub.2 A.sub.2 A.sub.4 A.sub.3 A.sub.5 A.sub.4 A.sub.6 A.sub.5 A.sub.7 A.sub.6 A.sub.8 A.sub.7 A.sub.9 A.sub.8 .sub. A.sub.10 A.sub.9 .sub. A.sub.11 .sub. A.sub.10 A.sub.1 .sub. A.sub.11 A.sub.3 ______________________________________

Claim 10

The system according to claim 4 wherein said image compressor means is comprised of: a first internal signal channel for said Y signal comprising: first averaging means receiving said Y signal for providing an average valve of a block of Y signal values; first comparing means for comparing each Y signal value in a block against the provided average value so as to generate a two-level bitmap signal; second averaging means for averaging all Y signals having a value corresponding to one level of said two-level bitmap; third averaging means for averaging all Y signals having a value corresponding to the second level of said two-level bitmap; and means for quantizing the averaged signals from said second and said third averaging means; a second internal signal channel for said I signal comprising: fourth averaging means for providing an average signal representing a block of I signal values; fifth averaging means for providing an average signal representing blocks of averaged signals from said fourth averaging means; second comparing for comparing each averaging signal from said fourth averaging means against the average signal from said fifth averaging means so as to generate a two-level bitmap; sixth averaging means for averaging all average signals from said fourth averaging means having a value corresponding to one level of said two-level bitmap; seventh averaging means for averaging all average signals from said fourth averaging means having a value corresponding to the second level of said two-level bitmap; and means for quantizing the averaged signals from said sixth and said seventh averaging means; a third internal signal channel for said Q signal comprising: eighth averaging means for averaging a block of Q signal values.

Claim 11

The system according to claim 8 wherein said image compressor means is further comprised of: a first demultiplexer means having an input coupled to receive said Y signal values, said demultiplexer responsive to the two-level bitmap signal from said first comparing means for directing said Y signal values to said second averaging means or said third averaging means as a function of the level of the two-level bit map signal; and a second demultiplexer means having an input coupled to receive the provided averaging signal from said fourth averaging means, said demultiplexer responsive to the two-level bitmap signal from said second comparing means for directing the provided averaging signal from said fourth averaging means to said sixth averaging means or said seventh averaging means as a function of the level of the two-level bit map signal.

Claim 12

The system according to claim 9 wherein said eight averaging means is comprised of: an accumulator for accumulating the values of all the Q signal values corresponding to a block; and means for dividing the accumulated values by the number of values in a block.