Programmable dynamic shift register with variable shift control

Claim 1

A data storage and delay circuit, comprising: a shift register having an input and a main output between which is disposed a first number of cells arranged in series, each said cell containing, at an initial time, a bit of an initial word having a first bit thereof in an input cell of said register and a last bit thereof in an output cell of said register, and clock means generating clock pulses at a predetermined frequency for shifting bits stored in said register from one cell to the next in the direction of the output of the register at said predetermined frequency; and control means synchronized to said initial time to enable a series of relevant bits including at least some consecutive bits of the initial word to be available bit by bit as an output of the register, from the beginning of an exploitation phase of the initial word; wherein the beginning of said phase is separated from the initial time by a time interval corresponding to the appearance of a predetermined number of clock pulses; and wherein the first one of said relevant bits is contained in a predetermined cell of said register at said initial time; said control means including at least one auxiliary register output, at which said series of relevant bits is made available; wherein said shift register comprises a dynamic register looped back on itself only by a connection of its main output with its input so as to enable a continuous recirculation of the digital data it contains; and wherein said auxiliary output is separated from said predetermined cell by a number of cells which is equal to said predetermined number, in the direction of the output of the register.