US4789862A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analogue to digital converters
Assignee: BAE Systems Defence Systems Ltd
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Filing: 1986-02-21
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Granted: 1988-12-06
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Expires: 2006-02-21
Abstract
Abstract A linear A to D converter comprising a combiner means to which an input signal to be converted is fed, the input signal being combined subtractively or additively with an analogue feedback signal, and the combiner means being arranged to feed an A to D flash converter via an amplifier, which A to D flash converter is arranged to feed a D to A converter which provides the feedback signal. The D to A converter comprises a digital overflowing accumulator also arranged to drive a finite impulse response filter having a plurality of serially coupled one bit delay elements, output signals from which are summed to provide the digital output signal.
Inventors
- 👤 Thomas Jackson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:18
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/39; H03M3/412; H03M3/422; H03M3/424; H03M3/428
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
182 words
An analogue to digital converter comprising first combiner means for receiving an analogue input signal, an analogue controller means for receiving an output from the first combiner means, a low resolution analogue to digital converter for receiving an output from the analogue controller means, a digital to analogue converter arranged in a feedback loop to the first combiner means, the digital to analogue converter comprising second combiner means for receiving a digital input from the low resolution analogue to digital converter, digital controller means for receiving an output from the second combiner means, digital slicer means for receiving an output from the digital controller means, feedback means for affording the output of the digital slicer means to the second combiner means and a finite impulse response filter connected to be driven by the output of the digital slicer means, the finite impulse response filter having a plurality of serially coupled delay elements, output signals from which are summed to provide the digital output signal and which serves also to provide the analogue feedback signal which is fed to the first combiner means.
Claim 2
Dependent Claim
182 words
An analogue to digital converter comprising first combiner means for receiving an analogue input signal, an analogue controller means for receiving an output from the first combiner means, a low resolution analogue to digital converter for receiving an output from the analogue controller means, a digital to analogue converter arranged in a feedback loop to the first combiner means, the digital to analogue converter comprising second combiner means for receiving a digital input from the low resolution analogue to digital converter, digital controller means for receiving an output from the second combiner means, digital slicer means for receiving an output from the digital controller means, feedback means for affording the output of the digital slicer means to the second combiner means and a finite impulse response filter connected to be driven by the output of the digital slicer means, the finite impulse response filter having a plurality of serially coupled delay elements, output signals from which are summed to provide the digital output signal and which serves also to provide the analogue feedback signal which is fed to the first combiner means.
Claim 3
Dependent Claim
19 words
An analogue to digital converter as claimed in claim 1 wherein the delay elements are one bit delay elements.
Claim 4
Dependent Claim
31 words
An analogue to digital converter as claimed in claim 1 wherein the first combiner means is a subtractor unit, the analogue input signal being subtractively combined with the analogue feedback signal.
Claim 5
Dependent Claim
39 words
An analogue to digital converter as claimed in claim 1 wherein the first combiner means is an adder, the analogue feedback signal being fed to the adder via an inverter to be additively combined with the analogue input signal.
References Cited (Backward Citations)
US3925731A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-12-06 | 1992-06-06 | 1992-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-12-06 | 1996-06-06 | 1996-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-12-06 | 2000-06-06 | 2000-12-06 | $7700.00 | Window Closed / Lapsed |