US4787686A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Monolithic programmable attenuator
Assignee: Raytheon Co
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Filing: 1987-02-17
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Granted: 1988-11-29
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Expires: 2007-02-17
Abstract
Abstract A programmable attenuator includes a plurality of field effect transistors (FETS) arranged together to provide an attenuation network. Each one of the FETS has a plurality of cell portions, each cell portion having drain, gate and source regions, the source and drain regions of the cell portions being connected in parallel. A first selected portion of the gate regions of each one of said FETS is connected to a gate electrode. A second selected remaining portion of the gate regions of each one of the FETS has the gate regions thereof physically isolated from the gate electrode. A signal fed to the gate electrode of each FET is distributed to the connected gate regions of each field effect transistor. In response to such signal, the total drain-source resistance of such FET is changed between a predetermined low value and a predetermined high value, with the resistance of the predetermined high value being determined, in part, by the number of such isolated gate regions.
Inventors
- 👤 Yusuke Tajima
- 👤 Toshikazu Tsukii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:50
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/24; H03H11/245
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
235 words
A radio frequency circuit having an input terminal and an output terminal comprising: a pair of field effect transistors, each transistor having drain, source and gate electrodes, with a first one of such drain and source electrodes of a first one of such pair of transistors being electrically coupled to the input terminal, a first one of such drain and source electrodes of a second one of the pair of transistors being electrically coupled to the output terminal, and the remaining one of drain and source electrodes of each one of the pair of transistors being electrically coupled at a common point; a third field effect transistor having a drain, source and gate electrodes with first one of such drain and source electrodes being electrically coupled with the aforementioned pair of transistors at the common point and the remaining one of such drain and source electrodes being electrically coupled to a reference potential; each field effect transistor having at least one pair of drain and source contacts disposed on a corresponding pair of drain and source regions and coupled to respective ones of the drain and source electrodes, and at least one gate contact disposed on a corresponding gate region between said pair of drain and source contacts; and wherein a selected portion of the gate region of each field effect transistor is physically separated from the gate contact having the gate electrode attached thereto.
Claim 2
Dependent Claim
235 words
A radio frequency circuit having an input terminal and an output terminal comprising: a pair of field effect transistors, each transistor having drain, source and gate electrodes, with a first one of such drain and source electrodes of a first one of such pair of transistors being electrically coupled to the input terminal, a first one of such drain and source electrodes of a second one of the pair of transistors being electrically coupled to the output terminal, and the remaining one of drain and source electrodes of each one of the pair of transistors being electrically coupled at a common point; a third field effect transistor having a drain, source and gate electrodes with first one of such drain and source electrodes being electrically coupled with the aforementioned pair of transistors at the common point and the remaining one of such drain and source electrodes being electrically coupled to a reference potential; each field effect transistor having at least one pair of drain and source contacts disposed on a corresponding pair of drain and source regions and coupled to respective ones of the drain and source electrodes, and at least one gate contact disposed on a corresponding gate region between said pair of drain and source contacts; and wherein a selected portion of the gate region of each field effect transistor is physically separated from the gate contact having the gate electrode attached thereto.
Claim 3
Dependent Claim
53 words
The radio frequency circuit as recited in claim 1 wherein each gate region physically separated from the gate contact of each field effect transistor is selected to provide a predetermined resistance between corresponding source and drain electrodes in response to a signal fed to the corresponding gate electrode of each field effect transistor.
Claim 4
Dependent Claim
38 words
The radio frequency circuit as recited in claim 2 wherein the predetermined resistance between source and drain electrodes of each field effect transistor is selected to provide, in combination, a predetermined impedance at said input and output terminals.
Claim 5
Dependent Claim
175 words
The radio frequency circuit as recited in claim 3 wherein a first set of voltage level signals is fed to the corresponding gate electrode of each one of the field effect transistors providing a first set of resistance values between drain and source electrodes of each one of such field effect transistors, and in response thereto, an input signal fed to the input terminal of the circuit appears at the output terminal of the circuit having an amplitude related to the first set of resistance values between said source and drain electrodes, and wherein a second different set of voltage level signals is fed to the corresponding gate electrode of each one of the field effect transistors providing a second different set of resistance values between source and drain electrodes, and in response thereto, an input signal fed to the input terminal of the circuit appears at the output terminal of the circuit with a second different amplitude related to the values of the second different set of resistance values between source and drain electrodes.
References Cited (Backward Citations)
US3621284A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-29 | 1992-05-30 | 1992-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-29 | 1996-05-30 | 1996-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-29 | 2000-05-30 | 2000-11-29 | $7700.00 | Window Closed / Lapsed |