Addressing multiple storage spaces

Claim 2

A data processing apparatus operating under program control in a first state, having a first domain of facilities within the apparatus including first domain storage space, or in a second state having a second domain of facilities within the apparatus including second domain storage space, for processing a sequence of instructions normally in the first state, the sequence of instructions including an instruction that results in a branch to the second state for execution of a program of instructions in the second domain, comprising: an instruction register, connected to receive instructions in the first and second states, including a plurality of fields, at least one field identifying a location for address information for an operand; decoding means, responsive to an instruction in the first state, for decoding the instruction to generate a control code, the control code including a branch signal and a domain access activation signal; means, connected to receive and responsive to the branch signal, for branching program control of the apparatus to the second state to enter the program of instructions in the second domain; interface means, responsive to the domain access activation signal and the one field in each instruction in the program of instructions, for generating a first domain access signal; addressing means, in communication with the instruction register, for supplying an address of an operand; and storage means, connected to receive the first domain access signal and the address, for storing operands at locations identified by addresses from the first and second domain storage spaces including means, responsive to the first domain access signal, for translating the address to first domain address space during processing of an instruction in the second state.

Claim 3

The apparatus of claim 1, wherein the location identified by the one field is a system general purpose register and the means for generating the first domain access signal includes: means for determining whether the general purpose register identified by the one field falls within a preselected range of general purpose registers.

Claim 4

The apparatus of claim 1, wherein the first state is a user state having access to user domain storage space and the second state is a control state having access to system storage space.

Claim 5

The apparatus of claim 1, wherein the program of instructions in the second domain emulates execution of an instruction in the first state.

Claim 6

The apparatus of claim 1, wherein the apparatus includes means for generating a program status word for controlling accesses to the storage means and the control code further includes a domain access control signal, further including:

Claim 7

domain access control register means, connected to receive the domain access control signal upon a branch to the second state, for holding the domain access activation signal and the domain access control signal during execution of the program of instructions in the second state; domain status register means, connected to receive a status indicator from the program status word for the instruction in the first state causing a branch to the second state, for holding the status indicator during execution of the program of instructions in the second state; and wherein the interface means is further in communication with the domain access control register means, the domain status register means and the storage means, for generating storage access control signals during execution of the program of instructions in the second state in response to the status indicator and the domain access control signal.

Claim 8

domain access control register means, connected to receive the domain access control signal upon a branch to the second state, for holding the domain access activation signal and the domain access control signal during execution of the program of instructions in the second state; domain status register means, connected to receive a status indicator from the program status word for the instruction in the first state causing a branch to the second state, for holding the status indicator during execution of the program of instructions in the second state; and wherein the interface means is further in communication with the domain access control register means, the domain status register means and the storage means, for generating storage access control signals during execution of the program of instructions in the second state in response to the status indicator and the domain access control signal.

Claim 9

The apparatus of claim 1, wherein the control code further includes a branch test signal, and further including: means, connected to receive the branch test signal, for testing for program exceptions upon a branch to the second state; and means, responsive to a program exception, for causing a branch to an alternative program of instructions.

Claim 10

A data processing apparatus operating under program control in a first state, having a first domain of facilities within the apparatus including first domain storage space, or in a second state, having a second domain of facilities within the apparatus including second domain storage space, for processing a sequence of instructions normally in the first state, the sequence of instructions including an instruction that results in a branch to the second state for execution of a program of instructions in the second domain, comprising: an instruction register, connected to receive instructions in the first and second states, including a plurality of fields, at least one field identifying a location for address information for an operand; decoding means, responsive to an instruction in the first state, for decoding the instruction to generate a control code including a branch signal and a domain access control signal; means, connected to receive and responsive to the branch signal, for branching program control of the apparatus to the second state to enter said program of instructions in the second domain; domain access control register means, connected to receive the domain access control signal upon a branch to the second state, for holding the domain access control signal during execution of the program of instructions in the second state; addressing means, in communication with the instruction register, for supplying an address of an operand; interface means, in communication with the domain access control register means, and the instruction register, for generating at least one access control signal during execution of the program of instructions in response to the domain access control signal and the one field of the instruction; storage means, connected to receive the address, for storing operands at locations identified by addresses from the first and second domain storage spaces including means, responsive to the access control signal for translating the address.

Claim 11

A data processing apparatus operating under program control in a first state, having a first domain of facilities within the apparatus including first domain storage space, or in a second state, having a second domain of facilities within the apparatus including second domain storage space, for processing a sequence of instructions normally in the first state, the sequence of instructions including an instruction that results in a branch to the second state for execution of a program of instructions in the second domain, comprising: an instruction register, connected to receive instructions in the first and second states, including a plurality of fields, at least one field identifying a location for address information for an operand; decoding means, responsive to an instruction in the first state, for decoding the instruction to generate a control code including a branch signal and a domain access control signal; means, connected to receive and responsive to the branch signal, for branching program control of the apparatus to the second state to enter said program of instructions in the second domain; domain access control register means, connected to receive the domain access control signal upon a branch to the second state, for holding the domain access control signal during execution of the program of instructions in the second state; addressing means, in communication with the instruction register, for supplying an address of an operand; interface means, in communication with the domain access control register means, and the instruction register, for generating at least one access control signal during execution of the program of instructions in response to the domain access control signal and the one field of the instruction; storage means, connected to receive the address, for storing operands at locations identified by addresses from the first and second domain storage spaces including means, responsive to the access control signal for translating the address.

Claim 12

The apparatus of claim 7, wherein the location identified by the one field is a system general purpose register and the interface means includes: means for determining whether the general purpose register identified by the one field falls within a preselected range of general purpose registers.

Claim 13

The apparatus of claim 7, wherein the first state is a user state having access to user domain storage space and the second state is a control state having access to system storage space.

Claim 14

The apparatus of claim 7, wherein the program of instructions in the second domain emulates execution of an instruction in the first state.

Claim 15

The apparatus of claim 7, wherein the apparatus includes means for generating a program status word for controlling accesses to the storage means, and further including: domain status register means, connected to receive a status indicator from the program status word for the instruction in the first state causing a branch to the second state, for holding the status indicator during execution of the program of instructions in the second state; and wherein the interface means is further in communication with the domain status register means and responsive to the status indicator for generating the storage access control signals.

Claim 16

The apparatus of claim 7, wherein the control code further includes a branch test signal, and further including: means, connected to receive the branch test signal, for testing for program exceptions upon a branch to the second state; and means, responsive to a program exception, for causing a branch to an alternative program of instructions.

Claim 17

A data processing apparatus operating under program control in a user state, having a user domain of facilities within the apparatus including domain storage space, or in a control state, having a system storage space, and having means for generating a program status word in response to execution of instruction for controlling accesses to the domain storage space and the system storage space, for processing a sequence of instructions normally in the user state, the sequence of instructions including an instruction that results in a branch to the control state for execution of an emulation program of instructions in the system storage space, comprising; an instruction register, connected to receive instructions in the user and control states, including a plurality of fields, at least one field identifying a location for address information for an operand; decoding means, responsive to an instruction in the user state, for decoding the instruction to generate a control code, the control code including a branch signal and a domain access control signal; means, connected to receive and responsive to the branch signal, for branching program control of the apparatus to the control state to enter the emulation program; domain access control register means, connected to receive the domain access control signal upon a branch to the control state, for holding the domain access control signal during execution of the emulation program; domain status register means, connected to receive a status indicator from the program status word for the instruction in the user state being emulated in the control state, for holding the status indicator during execution of the emulation program; and addressing means, in communication with the instruction register, for supplying an address of an operand; interface means, in communication with the domain access control register means the domain status register means, for generating at least one access control signal during execution of the emulation program of instructions in response to the status indicator and the domain access control signal; storage means, connected to receive the access control signal and the address, for storing operands at locations identified by addresses from the user domain storage space and system storage space including means, responsive to the access control signal for translating the address of said operand.

Claim 18

A data processing apparatus operating under program control in a user state, having a user domain of facilities within the apparatus including domain storage space, or in a control state, having a system storage space, and having means for generating a program status word in response to execution of instruction for controlling accesses to the domain storage space and the system storage space, for processing a sequence of instructions normally in the user state, the sequence of instructions including an instruction that results in a branch to the control state for execution of an emulation program of instructions in the system storage space, comprising; an instruction register, connected to receive instructions in the user and control states, including a plurality of fields, at least one field identifying a location for address information for an operand; decoding means, responsive to an instruction in the user state, for decoding the instruction to generate a control code, the control code including a branch signal and a domain access control signal; means, connected to receive and responsive to the branch signal, for branching program control of the apparatus to the control state to enter the emulation program; domain access control register means, connected to receive the domain access control signal upon a branch to the control state, for holding the domain access control signal during execution of the emulation program; domain status register means, connected to receive a status indicator from the program status word for the instruction in the user state being emulated in the control state, for holding the status indicator during execution of the emulation program; and addressing means, in communication with the instruction register, for supplying an address of an operand; interface means, in communication with the domain access control register means the domain status register means, for generating at least one access control signal during execution of the emulation program of instructions in response to the status indicator and the domain access control signal; storage means, connected to receive the access control signal and the address, for storing operands at locations identified by addresses from the user domain storage space and system storage space including means, responsive to the access control signal for translating the address of said operand.

Claim 19

The apparatus of claim 13, wherein the interface means further include: means responsive to the one field of the instruction register and at least a portion of the domain access control signal, for generating a user domain access signal; and means, in communication with the means for translating the address, responsive to the user domain access signal, for interpreting the address as a user domain address.

Claim 20

The apparatus of claim 14, wherein the location identified by the one field is a system general purpose register and the means for generating the access control signal includes: means for determining whether the general purpose register identified by the one field falls within a preselected range of general purpose registers.

Claim 21

A data processing apparatus operating under program control in a first state, having a first domain of facilities within the apparatus including first domain storage space, or in a second state having a second domain of facilities within the apparatus including second domain storage space, for processing a sequence of instructions normally in the first state, the sequence of instructions including an instruction that results in a branch to the second state of execution of a program of instructions in the second domain, comprising: first means, responsive to an instruction in the first state, for generating a plurality of fields, including a control code comprising a branch signal, a domain access activation signal, an address of an operand and at least a first field identifying a location for address information of the operand; interface means, responsive to the domain access activation signal and the first field in an instruction for generating a first domain access signal; and means coupled to said interface means and the first means, and responsive to the first domain access signal for translating the address to first domain address space during processing of an instruction in the second state.

Claim 22

A data processing apparatus operating under program control in a first state, having a first domain of facilities within the apparatus including first domain storage space, or in a second state having a second domain of facilities within the apparatus including second domain storage space, for processing a sequence of instructions normally in the first state, the sequence of instructions including an instruction that results in a branch to the second state of execution of a program of instructions in the second domain, comprising: first means, responsive to an instruction in the first state, for generating a plurality of fields, including a control code comprising a branch signal, a domain access activation signal, an address of an operand and at least a first field identifying a location for address information of the operand; interface means, responsive to the domain access activation signal and the first field in an instruction for generating a first domain access signal; and means coupled to said interface means and the first means, and responsive to the first domain access signal for translating the address to first domain address space during processing of an instruction in the second state.

Claim 23

The apparatus of claim 16, wherein the location identified by the first field is a system general purpose register and the means for generating the first domain access signal includes means for determining whether the general purpose register identified by the first field falls within a preselected range of general purpose registers.

Claim 24

The apparatus of claim 16, wherein the first state is a user state having access to user domain storage space and the second state is a control state having access to system storage space.

Claim 25

The apparatus of claim 16, wherein the program of instructions in the second domain emulates execution of an instruction in the first state.

Claim 26

The apparatus of claim 16, wherein the apparatus includes means for generating a program status word for controlling storage access and the control code further includes a domain access control signal, further including: domain access control register means, connected to receive the domain access control signal upon a branch to the second state, for holding the domain access activation signal and the domain access control signal during execution of the program of instructions in the second state; domain status register means, connected to receive a status indicator from the program status word for the instruction in the first state causing a branch to the second state, for holding the status indicator during execution of the program of instructions in the second state; and wherein the interface means is further in communication with the domain access control register means, the domain status register means for generating at least one access control signal during execution of the program of instructions in the second state in response to the status indicator and the domain access control signal.

Claim 27

The apparatus of claim 16, wherein the control code further includes a branch test signal, and further including: means, connected to receive the branch test signal, for testing for program exceptions upon a branch to the second state; and means, responsive to a program exception, for causing a branch to an alternative program of instructions.

Claim 28

A data processing apparatus operating under program control in a first state, having a first domain of facilities within the apparatus including first domain storage space, or in a second state, having a second domain of facilities within the apparatus including second domain storage space, for processing a sequence of instructions normally in the first state, the sequence of instructions including an instruction that results in a branch to the second state for execution of a program of instructions in the second domain, comprising: first means, responsive to an instruction in the first state, for generating a plurality of fields, including a control code comprising a branch signal and, a domain access control signal, an address of an operand and at least a first field identifying a location for address information of the operand; domain access control register means, connected to receive the domain access control signal upon a branch to the second state, for holding the domain access control signal during execution of the program of instructions in the second state; interface means, in communication with the domain access control register means, and the first means, for generating at least one access control signal during execution of the program of instructions in response to the domain access control signal and the first field of the instruction; and storage means coupled to said first means and responsive to the access control signal for translating the address of the operand.

Claim 29

A data processing apparatus operating under program control in a first state, having a first domain of facilities within the apparatus including first domain storage space, or in a second state, having a second domain of facilities within the apparatus including second domain storage space, for processing a sequence of instructions normally in the first state, the sequence of instructions including an instruction that results in a branch to the second state for execution of a program of instructions in the second domain, comprising: first means, responsive to an instruction in the first state, for generating a plurality of fields, including a control code comprising a branch signal and, a domain access control signal, an address of an operand and at least a first field identifying a location for address information of the operand; domain access control register means, connected to receive the domain access control signal upon a branch to the second state, for holding the domain access control signal during execution of the program of instructions in the second state; interface means, in communication with the domain access control register means, and the first means, for generating at least one access control signal during execution of the program of instructions in response to the domain access control signal and the first field of the instruction; and storage means coupled to said first means and responsive to the access control signal for translating the address of the operand.

Claim 30

The apparatus of claim 22, wherein the location identified by the first field is a system general purpose register and the interface means includes: means for determining whether the general purpose register identified by the first field falls within a preselected range of general purpose registers.

Claim 31

The apparatus of claim 22, wherein the first state is a user state having access to user domain storage space and the second state is a control state having access to system storage space.

Claim 32

The apparatus of claim 22, wherein the program of instructions in the second domain emulates execution of an instruction in the first state.

Claim 33

The apparatus of claim 22, wherein the apparatus includes means for generating a program status word for controlling accesses to the storage means, and further including: domain status register means, connected to receive a status indicator from the program status word for the instruction in the first state causing a branch to the second state, for storing the status indicator during execution of the program of instructions in the second state; and wherein the interface means is further in communication with the domain status register means and responsive to the status indicator for generating at least one storage control access signal.

Claim 34

The apparatus of claim 22, wherein the control code, further includes a branch test signal, and further including: means, connected to receive the branch test signal, for testing for program exceptions upon a branch to the second state; and means, responsive to a program exception, for causing a branch to an alternative program of instructions.

Claim 35

A data processing apparatus operating under program control in a user state, having a user domain of facilities within the apparatus including domain storage space, or in a control state, having a system storage space, and having means for generating a program status word in response to execution of instruction for controlling accesses to the domain storage space and the system storage space, for processing a sequence of instructions normally in the user state, the sequence of instructions including an instruction that results in a branch to the control state for execution of an emulation program of instructions in the system storage space, comprising: first means, responsive to an instruction in the user state, for decoding the instruction to generate a plurality of fields, including a control code comprising a domain access control signal, an address of an operand and at least one field identifying a location for address information of the operand; domain access control register measns, connected to receive the domain access control signal upon a branch to the control state, for holding the domain access control signal during execution of the emulation program; domain status register means, connected to receive a status indicator from the program status word for the instruction in the user state being emulated in the control state, for holding the status indicator during execution of the emulation program; and interface means, in communication with the domain access control register means, the domain status register means, for generating at least one access control signal during execution of the emulation program of instructions in response to the status indicator and the domain access control signal; and storage means, coupled to said first means and responsive to the access control signal, for translating the address of said operand.

Claim 36

A data processing apparatus operating under program control in a user state, having a user domain of facilities within the apparatus including domain storage space, or in a control state, having a system storage space, and having means for generating a program status word in response to execution of instruction for controlling accesses to the domain storage space and the system storage space, for processing a sequence of instructions normally in the user state, the sequence of instructions including an instruction that results in a branch to the control state for execution of an emulation program of instructions in the system storage space, comprising: first means, responsive to an instruction in the user state, for decoding the instruction to generate a plurality of fields, including a control code comprising a domain access control signal, an address of an operand and at least one field identifying a location for address information of the operand; domain access control register measns, connected to receive the domain access control signal upon a branch to the control state, for holding the domain access control signal during execution of the emulation program; domain status register means, connected to receive a status indicator from the program status word for the instruction in the user state being emulated in the control state, for holding the status indicator during execution of the emulation program; and interface means, in communication with the domain access control register means, the domain status register means, for generating at least one access control signal during execution of the emulation program of instructions in response to the status indicator and the domain access control signal; and storage means, coupled to said first means and responsive to the access control signal, for translating the address of said operand.

Claim 37

The apparatus of claim 28, wherein the interface means further include: means responsive to the one field of the instruction register and at least a portion of the domain access control signal, for generating a user domain access signal; and means, in communication with the means for translating the address, responsive to the user domain access signal, for interpreting the address as a user domain address.

Claim 38

The apparatus of claim 14, wherein the location identified by the one field is a system general purpose register and the means for generating the access control signals includes: means for determining whether the general purposes register identified by the one field falls within a preselected range of general purpose registers.