US4785251A
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Digital frequency and phase comparator
Assignee: Pioneer Corp
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Filing: 1987-01-21
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Granted: 1988-11-15
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Expires: 2007-01-21
Abstract
Abstract A digital frequency and phase comparator for both detecting a frequency of a digital signal and the phase thereof relative to a reference signal, wherein polarity inversions of the output phase different signal and saturated characteristics of the circuit when the phase difference succeeds a predetermined value are eliminated. The inventive digital frequency and phase comparator includes a time counter, an input holding circuit for holding a first and a second count value of the time counter at two different input timings of an input signal, a first arithmetic device for determining one of the frequency and period of the inputs signal in response to the first and second count values held by the input timing holding device, and a second arithmetic device for determining a phase of the input signal relative to a reference signal in response to a selected one of the first and second count values held in the input timing holding device.
Inventors
- 👤 Tetsuo Akiyama
- 👤 Satoshi Kusano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:42
CPC Classifications
G; G01; G01R; G01R25/00; G01R25/005; G01R23/00; G01R23/005; H; H03; H03K; H03K5/00; H03K5/22; H03K5/26
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
102 words
A digital frequency and phase comparator comprising: a time counter; input timing holding means for holding a first and a second count value of said time counter at two different input timings of an input signal; and arithmetic means for determining one of a frequency and a period of said input signal in response to said first and second count values held in said input timing holding means and for determining a phase of said input signal relative to a reference signal in response to a selected one of said first and second count values held in said input timing holding means.
Claim 2
Dependent Claim
102 words
A digital frequency and phase comparator comprising: a time counter; input timing holding means for holding a first and a second count value of said time counter at two different input timings of an input signal; and arithmetic means for determining one of a frequency and a period of said input signal in response to said first and second count values held in said input timing holding means and for determining a phase of said input signal relative to a reference signal in response to a selected one of said first and second count values held in said input timing holding means.
Claim 3
Dependent Claim
46 words
The digital frequency and phase comparator of claim 1, wherein said input timing holding means comprises: a latch circuit for latching a count value of said time counter at an input timing of said input signal, and means for storing an output of said latch circuit.
Claim 4
Dependent Claim
22 words
The digital frequency and phase comparator of claim 2, wherein values are obtained from said storing means and said latch circuit, respectively.
Claim 5
Dependent Claim
22 words
The digital frequency and phase comparator of claim 2, wherein said first and second count values are obtained from said storing means.
Claim 6
Dependent Claim
29 words
The digital frequency and phase comparator of claim 1, wherein said input timing holding means further comprises means for holding at least one input timing of said reference signal.
Claim 7
Dependent Claim
29 words
The digital frequency and phase comparator according to any one of claims 1 to 5, wherein said time counter comprises a free-running counter driven only by a single clock.
Claim 8
Dependent Claim
109 words
The digital frequency and phase comparator according to claim 1: wherein said input timing means further holds a third count value of said time counter at an input timing of said reference signal; wherein said arithmetic means determines said phase in response to said selected one of said first and second counts values and to said third count values; and further comprising switching means for selectively switching a control input of said input timing means between an input terminal carrying said input signal and an input terminal carrying said reference signal at a timing between said timing of said reference signal and said two timings of said input signal.
Claim 9
Dependent Claim
93 words
In a microprocessor programmed with a method for digital frequency and phase comparison, comprising the following steps: counting a time signal; holding a first count value and a second count value of said counting step at two different input timings of an input signal; arithmetically determining one of a frequency and a period of said input signal in response to said first and second count values; and arithmetically determining a phase of said input signal relative to a reference signal in response to a selected one of said first and second count values.
Claim 10
Dependent Claim
93 words
In a microprocessor programmed with a method for digital frequency and phase comparison, comprising the following steps: counting a time signal; holding a first count value and a second count value of said counting step at two different input timings of an input signal; arithmetically determining one of a frequency and a period of said input signal in response to said first and second count values; and arithmetically determining a phase of said input signal relative to a reference signal in response to a selected one of said first and second count values.
Claim 11
Dependent Claim
39 words
A method as recited in claim 8, wherein said holding step comprises the steps of: latching a count value of said counting step at an input timing of said input signal; and storing a result of said latching step.
Claim 12
Dependent Claim
19 words
A method as recited in claim 9, further comprising holding at least one input timing of said reference signal.
Claim 13
Dependent Claim
28 words
A method as recited in claim 10, wherein said step of arithmetically determining said phase is further in response to said one input timing of said reference signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-15 | 1992-05-16 | 1992-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-15 | 1996-05-16 | 1996-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-15 | 2000-05-16 | 2000-11-15 | $7700.00 | Window Closed / Lapsed |