Digital signal scrambler

Claim 2

A digital signal scrambler, comprised of: (a) means for receiving a digital input signal comprised of a plurality of bits, (b) a plurality of memory circuits for storing a plurality of intermediate scrambled digital signals, (c) means for addressing respective ones of said memory circuits with predetermined ones of said bits such that each of said memory circuits generates a predetermined one of said intermediate scrambled signals, and (d) a plurality of logic circuits for receiving said intermediate scrambled signals, performing an EXCLUSIVE OR function thereon and generating a scrambled digital output signal in response thereto, whereby a unique scrambled output signal is generated for each possible input signal according to the form of said stored intermediate scrambled signals.

Claim 3

A digital signal scrambler as defined in claim 1 wherein said memory circuits are storage registrs having respective data outputs thereof connected to respective inputs of said plurality of logic circuits.

Claim 4

A digital signal scrambler as defined in claim 2 wherein each of said logic circuits is comprised of an EXCLUSIVE OR gate.

Claim 5

A digital signal scrambler as defined in claim 1, wherein said digital input signal is comprised of 24 bits, said plurality of memory circuits is comprised of a pair of 4k byte random access memories, and said plurality of logic circuits is comprised of 24 2-input EXCLUSIVE OR gates having inputs connected to respective data outputs of each of said random access memories.

Claim 6

A digital signal scrambler as defined in claim 1, wherein said digital input signal is comprised of 24 bits, said plurality of memory circuits is comprised of three 256 byte random access memories, and said plurality of logic circuits is comprised of twenty-four 3-input EXCLUSIVE OR gates having inputs connected to respective data outputs of each of said random access memories.

Claim 7

A digital signal scrambler, comprised of: (a) means for receiving a digital input signal comprised of a plurality of bits denoted as N, (b) a plurality of memory circuits for storing a plurality of intermediate scrambled digital signals each comprised of N bits, (c) means for addressing respective ones of said memory circuits with predetermined bits of said plurality of bits comprising said digital input signal, such that each of said memory circuits generates a predetermined one of said intermediate scrambled signals, and (d) a plurality of logic circuits equal in number to N, each logic circuit having a plurality of inputs equal in number to said plurality of memory circuits, connected to respective outputs of said memory circuits, for receiving said intermediate scrambled signals, performing EXCLUSIVE OR functions thereon, and generating a scrambled digital output signal having N bits in response thereto, whereby a unique scrambled output signal is generated for each possible input signal according to the form of said stored intermediate scrambled signals.

Claim 8

A digital signal scrambler, comprised of: (a) means for receiving a digital input signal comprised of a plurality of bits denoted as N, (b) a plurality of memory circuits for storing a plurality of intermediate scrambled digital signals each comprised of N bits, (c) means for addressing respective ones of said memory circuits with predetermined bits of said plurality of bits comprising said digital input signal, such that each of said memory circuits generates a predetermined one of said intermediate scrambled signals, and (d) a plurality of logic circuits equal in number to N, each logic circuit having a plurality of inputs equal in number to said plurality of memory circuits, connected to respective outputs of said memory circuits, for receiving said intermediate scrambled signals, performing EXCLUSIVE OR functions thereon, and generating a scrambled digital output signal having N bits in response thereto, whereby a unique scrambled output signal is generated for each possible input signal according to the form of said stored intermediate scrambled signals.

Claim 9

A digital signal scrambler as defined in claim 6, wherein N equals 24, said plurality of memory circuits is comprised of a pair of 4k byte random access memories, and said plurality of logic circuits is comprised of twenty four 2-input EXCLUSIVE OR gates having inputs connected to respective outputs of each of said random access memories.

Claim 10

A digital signal scrambler as defined in claim 6, wherein N equals 24, said plurality of memory circuits is comprised of three 256 byte random access memories, and said plurality of logic circuits is comprised of twenty four 3-input EXCLUSIVE OR gates having inputs connected to respective data outputs of each of said random access memories.

Claim 11

A digital signal scrambler as defined in claim 6, wherein said digital input signal is comprised of an X and Y coordinate address signal for addressing a predetermined memory cell in a random access memory, and said scrambled digital output signal is a scrambled address signal for application to said random access memory which in response descrambles said scrambled signal according to a predetermined characteristic topological scrambling function and accesses said predetermined memory cell.

Claim 12

A digital signal scrambler as defined in claim 6, wherein said digital input signal is a data signal for storage in a predetermined one or more memory cells of a random access memory, and said scrambled digital output signal is a scrambled data signal for application to said random access memory which in response descrambles said scrambled signal according to a predetermined characteristic topological scrambling function and stores said data signal in said predetermined one or more memory cells.

Claim 13

A digital signal scrambler as defined in claim 6 wherein said memory circuits are storage registers having respective data outputs connected to respective inputs of said plurality of logic circuits.

Claim 14

A digital signal scrambler as defined in claim 11 wherein N equals 24, said plurality of memory circuits is comprised of a pair of 4k byte random access memories, and said plurality of logic circuits is comprised of twenty four 2-input EXCLUSIVE OR gates having inputs connected to respective outputs of each of said random access memories.

Claim 15

A digital signal scrambler as defined in claim 11 wherein N equals 24, said plurality of memory circuits is comprised of three 256 byte random access memories, and said plurality of logic circuits is comprised of twenty four 3-input EXCLUSIVE OR gates having inputs connected to respective data outputs of each of said random access memories.

Claim 16

A digital signal scrambler as defined in claim 11 wherein said digital input signal is comprised of an X and Y coordinate address signal for addressing a predetermined memory cell in a random access memory, and said scrambled digital output signals is a scrambled address signal for application to said random access memory which in response descrambles said scrambled signal according to a predetermined characteristic topological scrambling function and accesses said predetermined memory cell.

Claim 17

A digital signal scrambler as defined in claim 11 wherein said digital input signal is a data signal for storage in a predetermined one or more memory cells of a random access memory, and said scrambled digital output signal is a scrambled data signal for application to said random access memory which in response descrambles said scrambled signal according to a predetermined characteristic topological scrambling function and stores said data signal in said predetermined one or more memory cells.

Claim 18

A digital signal scrambler as defined in claim 11 wherein each of said logic circuits is comprised of an EXCLUSIVE OR gate.

Claim 19

A digital signal scrambler as defined in claim 16 wherein N equals 24, said plurality of memory circuits is comprised of a pair of 4k byte random access memories, and said plurality of logic circuits is comprised of twenty four 2-input EXCLUSIVE OR gates having inputs connected to respective outputs of each of said random access memories.

Claim 20

A digital signal scrambler as defined in claim 16 wherein N equals 24, said plurality of memory circuits is comprised of three 256 byte random access memories, and said plurality of logic circuits is comprised of twenty four 3-input EXCLUSIVE OR gates having inputs connected to respective data outputs of each of said random access memories.

Claim 21

A digital signal scrambler as defined in claim 16 wherein said digital input signal is comprised of an X and Y coordinate address signal for addressing a predetermined memory cell in a random access memory, and said scrambled digital output signal is a scrambled address signal for application to said random access memory which in response descrambles said scrambled signal according to a predetermined characteristic topological scrambling function and accesses said predetermined memory cell.

Claim 22

A digital signal scrambler as defined in claim 16 wherein said digital input signal is a data signal for storage in a predetermined one or more memory cells of a random access memory, and said scrambled digital ouput signal is a scrambled data signal for application to said random access memory which in response descrambles said scrambled signal according to a predetermined characteristic topological scrambling function and stores said data signal in said predetermined one or more memory cells.