Electronic digital crossconnect system

Claim 1

In an electric digital crossconnect system for interconnecting a plurality of high frequency T-carrier lines, each having an input line and an output line, comprising: a plurality of means for interfacing with the input and output lines of the T-carrier lines, each means for interfacing connected to a predetermined one of the T-carrier lines and having an output port and an input port wherein said means for interfacing comprises, receive T-1 interface connected to said incoming T-1 line; receive frame alignment module connected to said T-1 interface; signalling reinsertion module connected to said receive frame alignment module; address counter timing generator module connected to said receive frame alignment module and to said signalling reinsertion module; trunk conditioning function connected to said address counter generator module and to said outgoing information bus and to said transmit T-1 interface; master controller interface connected to said trunk conditioning function and to said receive frame alignment module; transmit T-1 interface connected to said address counter and timing generator and to said trunk conditioning function and connected to the T-1 outgoing line; wherein said incoming information bus is connected to said signalling reinsertion module said receive frame alignment module and said receive T-1 interface; means for providing time slot interchanges having at least one input port, at least one output port; means for providing an incoming information bus connected between each of said output ports of said means for interfacing and said input port of said means for providing time slot interchanges; means for providing an outgoing information bus connected between each of said input ports of said means for interfacing and said output port of said means for providing time slot interchanges; means for controlling connected via a provisioning data link to each of said master controller interface and to said means for time slot interchanging; wherein signals received from the input lines of the T-carrier lines by the means for interfacing are placed in pre-determined time slots on the incoming information bus means and wherein the means for time slot interchanging reorders the signal in time slots on said outgoing information bus means so at the signals can be sent out on predetermined output lines of the T-carrier lines by means for interfacing.

Claim 3

The system defined in claim one wherein said means for interfacing are divided into N sets of M means for interfacing and wherein said means for time slot interchanges has N input ports and N output ports and wherein said means for providing an incoming information bus comprises N incoming individual busses and wherein said means for providing an outgoing information bus comprises N outgoing individual buses such that each of said incoming individual busses connects all of said output ports of the respective set of means of interfacing to the corresponding input port of said means for time slot interchanging and such that each of said outoing individual busses connects the corresponding output port of said means for time slot interchanging to all of said input ports of the respective set of means for interfacing.

Claim 4

The system defined in claim two wherein each of said means for interfacing has an address counter slaved to an address counter in said means for time slot interchanging.

Claim 5

The system defined in claim two wherein each of said means for interfacing has a means for signalling reinsertion such that signalling reinsertion occurs prior to output to the incoming information bus, whereby special leads for signalling bits are eliminated from the incoming information bus.

Claim 6

The system defined in claim two wherein said means for providing time slot interchanging comprises: means for multiplexing, connected to said incoming individual busses and connected to a first high-speed information bus, said means for multiplexing combining said incoming individual busses into said high-speed information bus; means for providing an information memory having first and second sections and connected to said incoming high speed information bus; means for providing predetermined addresses connected to said information memory; means for providing a connection memory connected to said information memory; means for providing a demultiplexer connected to an outgoing high speed information bus which is connected to said information memory, said means for providing a demultiplexer connected to said outgoing individual busses such that said outgoing high speed information bus is split between said outgoing individual busses.

Claim 7

The system defined in claim one wherein said means for interfacing are divided into first and second sets, and wherein said means for time slot interchanges has first and second input ports and first and second output ports, and wherein said means for providing an incoming information bus and said means for providing an outgoing information bus are split such that first incoming and first outgoing information busses are provided between said means for time slot interchanging and said first set of said means for interfacing, and second incoming and second outgoing information busses are provided between said means for time slot interchanging and said second set of means for interfacing.