US4780896A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed digital counter slip control circuit
Assignee: Siemens Transmission Systems Inc
•
Filing: 1987-02-09
•
Granted: 1988-10-25
•
Expires: 2007-02-09
Abstract
Abstract A counter slip control circuit is described for digital transmission systems wherein the counter uses a feedback circuit to define the permissible counter states. The slip control input modifies the feedback function so that certain counter states are either repeated or skipped. A repeated counter state is equivalent to retardation of the counter output signal phase. A skipped counter state is equivalent to advancing the counter output signal phase. The slip control gate is eliminated from the clock input line to the counter and instead is included in the feedback path which eliminates the skew problem and permits the equivalent of adding clock pulses without the requirement for logic speeds of twice the normal clock speed.
Inventors
- 👤 Berton E. Dotter, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:23
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/667
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
104 words
A counter slip control circuit for high speed digital logic, comprising: digital counter means for deriving an output signal and having a plurality of counter states and having a clock input; counter feedback circuit means for forcing desired counter states to occur at desired times in synchronism with a signal at said clock input; slip control input means for receiving a slip control input pulse; and feedback modification circuit means responsive to the slip control input means, and having an output coupled to said counter feedback circuit means, such that a counter state is repeated, thereby retarding the phase of the counter output signal.
Claim 2
Dependent Claim
104 words
A counter slip control circuit for high speed digital logic, comprising: digital counter means for deriving an output signal and having a plurality of counter states and having a clock input; counter feedback circuit means for forcing desired counter states to occur at desired times in synchronism with a signal at said clock input; slip control input means for receiving a slip control input pulse; and feedback modification circuit means responsive to the slip control input means, and having an output coupled to said counter feedback circuit means, such that a counter state is repeated, thereby retarding the phase of the counter output signal.
Claim 3
Dependent Claim
20 words
A counter slip control circuit in accordance with claim 1, wherein said retarding is equivalent to one clock time period.
Claim 4
Dependent Claim
18 words
A counter slip control circuit in accordance with claim 1, wherein the digital counter is a ring counter.
Claim 5
Dependent Claim
26 words
A counter slip control circuit in accordance with claim 3 wherein said ring counter comprises a plurality of stages, each stage consisting of a flip-flop circuit.
Claim 6
Dependent Claim
104 words
A counter slip control circuit for high speed digital logic, comprising: digital counter means for deriving an output signal and having a plurality of counter states and having a clock input; counter feedback circuit means for forcing desired counter states to occur at desired times in synchronism with a signal at said clock input; slip control input means for receiving a slip control input pulse; and feedback modification circuit means responsive to the slip control input means and having an output coupled to said counter feedback circuit means, such that a counter state is skipped, thereby advancing the phase of the counter output signal.
Claim 7
Dependent Claim
104 words
A counter slip control circuit for high speed digital logic, comprising: digital counter means for deriving an output signal and having a plurality of counter states and having a clock input; counter feedback circuit means for forcing desired counter states to occur at desired times in synchronism with a signal at said clock input; slip control input means for receiving a slip control input pulse; and feedback modification circuit means responsive to the slip control input means and having an output coupled to said counter feedback circuit means, such that a counter state is skipped, thereby advancing the phase of the counter output signal.
Claim 8
Dependent Claim
18 words
A counter slip control circuit in accordance with claim 5, wherein the digital counter is a ring counter.
Claim 9
Dependent Claim
26 words
A counter slip control circuit in accordance with claim 6, wherein said ring counter comprises a plurality of stages, each stage consisting of a flip-flop circuit.
Claim 10
Dependent Claim
23 words
A counter slip control circuit in accordance with claim 5 wherein said feedback modification circuit includes means for defining the permissible counter states
References Cited (Backward Citations)
US3571794A
Cited
US3618036A
Cited
US3800233A
Cited
US3673501A
Cited
US3867579A
Cited
US4101838A
Cited
US4184068A
Cited
US4175287A
Cited
US4368531A
Cited
US4561250A
Cited
US4394769A
Cited
US4573175A
Cited
EP0156213A2
Cited
US4580279A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-25 | 1992-04-25 | 1992-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-25 | 1996-04-25 | 1996-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-25 | 2000-04-25 | 2000-10-25 | $7700.00 | Window Closed / Lapsed |