US4779072A
Expired / Lapsed
US
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Channel encoder
Assignee: US Philips Corp
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Filing: 1987-06-15
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Granted: 1988-10-18
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Expires: 2007-06-15
Abstract
Abstract On the basis of n-bit words presented, the described channel encoder generates DC-free and run length limited m-bit (m n) code words having (1 + D)<-><1> or (1 + D<2>)<-><1> precoder properties. The m-bit code words are formed each time by appending (m-n) bits to the n-bit words presented. For the determination of the (m-n) bits to be added, the amplitude density function as well as the distribution of the run length and the digital sum variation of the code words is calculated.
Inventors
- 👤 Wilhelmus J. van Gestel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:43
CPC Classifications
H; H03; H03M; H03M7/00; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426; H03M5/00; H03M5/02; H03M5/04; H03M5/14; H03M5/145
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
229 words
A channel encoder for encoding received n-bit information words into m-bit, mainly DC-free, code words, where m>n, said channel encoder comprising: a. a precoder having a transfer function (1+D m-n ) -1 , where D is a delay operator, said precoder having an input for receiving said n-bit information words in series with (m-n)-bit words and an output for supplying said m-bit code words, said precoder forming said m-bit code words from said n-bit information words and said (m-n)-bit words, so that said m-bit code words are run length limited; b. a counter for determining a digital sum variation (DSV) between two successive m-bit code words, said counter having an input coupled with the output of said precoder for receiving said m-bit code words, and an output at which said digital sum variation is provided; and c. a memory circuit having a first input coupled with the output of the counter for receiving said digital sum variation, a second input for receiving said n-bit information words, and a third input coupled with said precoder for receiving said m-bit code words, said memory circuit forming a digital sum value of said m-bit code words and forming said (m-n)-bit words by logically combining said digital sum value with said digital sum variation and (m-n) bits of received m-bit code words, said memory circuit having an output for supplying said (m-n)-bit words.
Claim 2
Dependent Claim
229 words
A channel encoder for encoding received n-bit information words into m-bit, mainly DC-free, code words, where m>n, said channel encoder comprising: a. a precoder having a transfer function (1+D m-n ) -1 , where D is a delay operator, said precoder having an input for receiving said n-bit information words in series with (m-n)-bit words and an output for supplying said m-bit code words, said precoder forming said m-bit code words from said n-bit information words and said (m-n)-bit words, so that said m-bit code words are run length limited; b. a counter for determining a digital sum variation (DSV) between two successive m-bit code words, said counter having an input coupled with the output of said precoder for receiving said m-bit code words, and an output at which said digital sum variation is provided; and c. a memory circuit having a first input coupled with the output of the counter for receiving said digital sum variation, a second input for receiving said n-bit information words, and a third input coupled with said precoder for receiving said m-bit code words, said memory circuit forming a digital sum value of said m-bit code words and forming said (m-n)-bit words by logically combining said digital sum value with said digital sum variation and (m-n) bits of received m-bit code words, said memory circuit having an output for supplying said (m-n)-bit words.
Claim 3
Dependent Claim
201 words
A channel encoder for encoding received n-bit information words into m-bit, mainly DC-free, code words, where m>n, the channel encoder comprising: a. a precoder having a transfer function (1+D) -1 and forming said m-bit code words from said n-bit information words and from (m-n)-bit words, so that said m-bit code words are run length limited, said precoder having an input for receiving said n-bit information words in series with said (m-n)-bit words and an output at which said m-bit code words are provided, where (m-n)=1, and D is a delay operator; b. a counter for determining a digital sum variation (DSV) between two successive m-bit code words, said counter having an input coupled with the output of said precoder for receiving said m-bit code words, and an output at which said digital sum variation is provided; c. a memory circuit having a first input coupled with the counter for receiving said digital sum variation, a second input for receiving said n-bit information words, and a third input for receiving a last bit of said m-bit code words, said memory circuit forming the (m-n)-bit words from said digital sum variation, said m-bit information words and said last bit of said code words.
Claim 4
Dependent Claim
201 words
A channel encoder for encoding received n-bit information words into m-bit, mainly DC-free, code words, where m>n, the channel encoder comprising: a. a precoder having a transfer function (1+D) -1 and forming said m-bit code words from said n-bit information words and from (m-n)-bit words, so that said m-bit code words are run length limited, said precoder having an input for receiving said n-bit information words in series with said (m-n)-bit words and an output at which said m-bit code words are provided, where (m-n)=1, and D is a delay operator; b. a counter for determining a digital sum variation (DSV) between two successive m-bit code words, said counter having an input coupled with the output of said precoder for receiving said m-bit code words, and an output at which said digital sum variation is provided; c. a memory circuit having a first input coupled with the counter for receiving said digital sum variation, a second input for receiving said n-bit information words, and a third input for receiving a last bit of said m-bit code words, said memory circuit forming the (m-n)-bit words from said digital sum variation, said m-bit information words and said last bit of said code words.
Claim 5
Dependent Claim
74 words
A channel encoder as claimed in claim 2, characterized in that the memory circuit comprises a memory wherein there is stored the digital sum for each of the m-bits code words having passed the precoder following an m-bits codeword which last bit has a first predetermined value and which m-bits codewords being formed each time from a respective n-bits information word to which a 1-bit word having a second predetermined value has been appended.
Claim 6
Dependent Claim
94 words
A channel encoder as claimed in claim 3, characterized in that the memory circuit also includes a logic circuit connected to a data output of said memory and having the transfer function y=x.sub.1 x.sub.2 x.sub.3 +x.sub.1 x.sub.2 x.sub.3 +x.sub.1 x.sub.2 x.sub.3 +x.sub.1 x.sub.2 x.sub.3 where x 1 represents a standard for the relevant digital sum value (DS), x 2 represents said last bit supplied by the precoder, and x 3 represents a standard for said digital sum variation (DSV), y being the value of the bit to be appended to the n-bit information word.
Claim 7
Dependent Claim
69 words
A channel encoder as claimed in claim 4, characterized in that said encoder comprises a zero detector whereto the n-bit information word is applied and which supplies a zero detection signal when the n-bit information word consists only of zeroes, said zero detection signal respectively said signal y being applied to a first respectively a second input of a logic OR-gate at which output said 1-bit word being supplied.
Claim 8
Dependent Claim
212 words
A channel encoder for encoding received n-bit information words into m-bit, mainly DC-free, code words, where m>n, the channel encoder comprising: a. a precoder having a transfer function (1+D 2 ) -1 and forming said m-bit code words from said n-bit information words and from (m-n) bit words, so that said m-bit code words are run length limited, said precoder having an input for receiving said n-bit information words in series with said (m-n)-bit words and an output at which said m-bit code words are provided, where (m-n)=2, and D is a delay operator; b. a counter for determining a digital sum variation (DSV) between two successive m-bit code words, said counter having an input coupled with the output of said precoder for receiving said m-bit code words, and an output at which said digital sum variation is provided; and c. a memory circuit having a first input coupled with the counter for receiving said digital sum variation, a second input for receiving said n-bit information words, and a third input for receiving a last two bits (x m ,x m-1 ) of said m-bit code words, said memory circuit forming the (m-n)-bit words from said digital sum variation, said m-bit information words and said last two bits of said code words.
Claim 9
Dependent Claim
212 words
A channel encoder for encoding received n-bit information words into m-bit, mainly DC-free, code words, where m>n, the channel encoder comprising: a. a precoder having a transfer function (1+D 2 ) -1 and forming said m-bit code words from said n-bit information words and from (m-n) bit words, so that said m-bit code words are run length limited, said precoder having an input for receiving said n-bit information words in series with said (m-n)-bit words and an output at which said m-bit code words are provided, where (m-n)=2, and D is a delay operator; b. a counter for determining a digital sum variation (DSV) between two successive m-bit code words, said counter having an input coupled with the output of said precoder for receiving said m-bit code words, and an output at which said digital sum variation is provided; and c. a memory circuit having a first input coupled with the counter for receiving said digital sum variation, a second input for receiving said n-bit information words, and a third input for receiving a last two bits (x m ,x m-1 ) of said m-bit code words, said memory circuit forming the (m-n)-bit words from said digital sum variation, said m-bit information words and said last two bits of said code words.
Claim 10
Dependent Claim
87 words
A channel encoder as claimed in claim 6, characterized in that in the memory circuit is provided for forming a 2-bit word (x a , x b ) upon reception of the n-bit information word and said digital sum variation, the memory circuit further comprises two EXCLUSIVE-OR gates which, in response to the bits x a and x b and to the bits x m and x m-1 , supply the bits x' a and x' b , respectively, to be added to the n-bit information word.
Claim 11
Dependent Claim
101 words
A channel encoder as claimed in claim 7, characterized in that the memory circuit comprises a first sub-memory which determines a first partial digital sum value (DS a ) in response to the even bits of the n-bit information word, a second sub-memory which supplies a second partial digital sum value (DS b ) in response to the odd bits of the n-bit information word, and a third sub-memory which derives said 2-bit word (x a , x b ) from the first and the second partial digital sum value (DS a , DS b ) and the digital sum variation.
Claim 12
Dependent Claim
90 words
A channel encoder as claimed in claim 8, characterized in that in the first and the second sub-memory there are stored digital sum values (DS a , DS b ) which have been formed by appending each time the 1-bit word x' a , x' b , respectively, having a predetermined value, to said even bits and odd bits, respectively, the combination thus obtained passed the precoder, the last two bits of fixed value of the preceding m-bit code word supplied by the precoder having been applied to the precoder.
References Cited (Backward Citations)
US4499454A
Cited
US4598267A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-18 | 1992-04-18 | 1992-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-18 | 1996-04-18 | 1996-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-18 | 2000-04-18 | 2000-10-18 | $7700.00 | Window Closed / Lapsed |