US4779059A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current mirror circuit
Assignee: NEC Corp
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Filing: 1987-07-06
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Granted: 1988-10-18
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Expires: 2007-07-06
Abstract
Abstract A current mirror circuit including an operational amplifier connected to transistors of the current mirror circuit such that operating points of the transistors, that is, the emitter electrodes, are at the same potential. Thus, resistors connected between those emitters and an output of the operational amplifier may be increased even when the transistors are implemented in an integrated circuit. As a result, even with this configuration, current mirror accuracy may be improved.
Inventors
- 👤 Yoichiro Taki
- 👤 Yoshiaki Kawada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:09
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
113 words
A current mirror circuit comprising: first and second transistors, each having a base electrode, a collector electrode, and an emitter electrode, said base electrodes of said first and second transistors being connected to each other; an operational amplifier having inverted and non-inverted input terminals and an output terminal, said inverted input terminal being connected to said emitter electrode of said first transistor, and said non-inverted terminal being connected to a reference voltage; a first resistor disposed between said output terminal of said operational amplifier and said emitter electrode of said first transistor; and a second resistor disposed between said output terminal of said operational amplifier and said emitter electrode of said second transistor.
Claim 2
Dependent Claim
113 words
A current mirror circuit comprising: first and second transistors, each having a base electrode, a collector electrode, and an emitter electrode, said base electrodes of said first and second transistors being connected to each other; an operational amplifier having inverted and non-inverted input terminals and an output terminal, said inverted input terminal being connected to said emitter electrode of said first transistor, and said non-inverted terminal being connected to a reference voltage; a first resistor disposed between said output terminal of said operational amplifier and said emitter electrode of said first transistor; and a second resistor disposed between said output terminal of said operational amplifier and said emitter electrode of said second transistor.
Claim 3
Dependent Claim
35 words
The current mirror circuit as claimed in claim 1, wherein said first and second transistors are included in an integrated circuit, and said first and second resistors are connected to terminals of said integrated circuit.
Claim 4
Dependent Claim
35 words
The current mirror circuit as claimed in claim 1, further comprising a multiplier connected to said collector electrodes of said first and second transistors, said multiplier including third and fourth transistors and a current source.
References Cited (Backward Citations)
US3922614A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-18 | 1992-04-18 | 1992-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-18 | 1996-04-18 | 1996-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-18 | 2000-04-18 | 2000-10-18 | $7700.00 | Window Closed / Lapsed |