Apparatus for deskewing successively occurring blocks of data

Claim 2

A circuit for deskewing successively occurring blocks of data from two channels wherein overlap in time may occur between the end of a first block of data from a first channel relative to the beginning of a second block of data from a second channel, comprising: means for supplying memory read and write control signals, said read control signal being independent of the write control signal; memory means in said first and second channels for receiving the first and second data blocks respectively, for alternately storing the successive data blocks in response to the write control signal; and data control means for determining the occurrence of overlap between the successive data blocks and for inhibiting the read control signal from reading the second data block from the memory means for a delay time period corresponding to any overlap.

Claim 3

The circuit of claim 1 including: means for providing off-tape timing signals to the data control means which are indicative of the timing of the alternately stored blocks of data; and wherein said data control means enables read out of the first stored block of data in the first channel via the read control signal and thereafter enables the read out of the second stored clock of data in the second channel at the end of the delay time period.

Claim 4

The circuit of claim 2 wherein: said memory means includes first and second memories in the first and second channels, for alternately storing the first and second blocks of data respectively in response to the write control signal; an said data control means includes first and second data selector control circuits in the first and second channels, for receiving the off-tape timing signals for determining thereform any data block overlap.

Claim 5

The circuit of claim 3 wherein the first and second data selector control circuits include: pass circuit means for supplying an activate signal indicative of the number of horizontal television lines in each block of data; and means responsive to the pass circuit means for further inhibiting the reading of data from a memory in response to the activate signal.

Claim 6

The circuit of claim 4 wherein the first and second data selector control circuits include: write-to-read transfer circuit means for receiving the off-tape timing signals and the activate signal and for enabling the reading of data from a memory in response to both the timing and activate signals.

Claim 7

The circuit of claim 3 further including: data selector means coupled to the first and second memories in the first and second channels, for selecting the respective blocks of data from alternate channels in response to the read control signals of the first and second data selector control circuits.

Claim 8

A circuit for deskewing successively occurring first and second data signals in first and second channels respectively, comprising: first memory means in the first channel for storing the first data signal; second memory means in the second channel for storing the second data signal; data selector control means for generating a delayed switching signal indicative of any overlap in time between the occurrence of the second data signal relative to the first data signal; and data selector means responsive to the data selector control means for selecting the first data signal from the first memory means, and then selecting the second data signal from the second memory means in response to the delayed switching signal.

Claim 9

A circuit for deskewing successively occurring first and second data signals in first and second channels respectively, comprising: first memory means in the first channel for storing the first data signal; second memory means in the second channel for storing the second data signal; data selector control means for generating a delayed switching signal indicative of any overlap in time between the occurrence of the second data signal relative to the first data signal; and data selector means responsive to the data selector control means for selecting the first data signal from the first memory means, and then selecting the second data signal from the second memory means in response to the delayed switching signal.

Claim 10

The circuit of claim 7 wherein the data selector control means includes: means for supplying off-tape timing signals indicative of any overlap between the stored first and second data signals; and read control means receiving the off-tape timing signals for generating the delayed switching signal in response to the extent of any overlap between the data signals.

Claim 11

The circuit of claim 8 wherein the data selector control means further include: pass counter means for supplying an activate signal indicative of the time period of each of the first and second data signals; and said read control means being further responsive to the activate signal when generating the delayed switching signal.

Claim 12

The circuit of claim 8 wherein the read control means includes first and second circuits integral within the data selector control means for respectively supplying a first read enable signal to read out the second data signal and a second read enable signal to read out the first data signal, said first and second read enable signals being further responsive to the delayed switching signal in the event of an overlap.

Claim 13

The circuit of claim 7 wherein: said first and second memory means include respective write enable circuits, and respective read enable circuits which are independent of the write enable circuits; and said data selector control means include first and second selector control circuits for supplying selected control signals to the first and second write and read enable circuits respectively.

Claim 14

The circuit of claim 11 wherein the first and second selector control circuits respectively include: first and second write control means for loading the successive first and second data signals into respective first and second memory means as the data signals are received; first read control means for reading the stored first data signal from the first memory means while inhibiting the read out of the stored second data signal; and second read control means for reading the stored second data signal from the second memory means while inhibiting the read out of the stored first data signal.

Claim 15

The circuit of claim 12 wherein the first and second read control means respectively include: a first transfer circuit for enabling the first read enable circuit after the first write enable circuit has loaded the first memory means; a second transfer circuit for enabling the second read enable circuit after the second write enable circuit has loaded the second memory means; a first read stop circuit for inhibiting the second transfer circuit as long as the first transfer circuit enables the first read enable circuit; and a second read stop circuit for inhibiting the first transfer circuit as long as the second transfer circuit enables the second read enable circuit.

Claim 16

The circuit of claim 13 wherein the first and second read control means further respectively include: first and second pass circuit means respectively coupled to the first and second transfer circuits and to the first and second read stop circuits for supplying thereto respective activate signals indicative of the time period of each of the first and second data signals.

Claim 17

A circuit for deskewing successive blocks of data recovered along with respective data block timing signals by multiple playback heads in respective channels, wherein the blocks of data include a selected number of television lines corresponding to each pass of the heads, and wherein overlap in time may occur between successive blocks of data being recovered via respective channels, comprising: a first memory unit for storing a first data block in a first channel; a second memory unit for storing a second data block in a second channel; a first selector control circuit coupled to the first memory unit for loading the first data block in response to its timing signal; a second selector control circuit coupled to the second memory unit for loading the second data block in response to its timing signal; said first and second selector control circuits including respective first and second circuit means for determining any overlap between the first and second stored data blocks; and data selector means coupled to the first and second memory units for selecting respective data blocks alternately from the channels one at a time in response to the determined overlap by the first and second circuit means.

Claim 18

A circuit for deskewing successive blocks of data recovered along with respective data block timing signals by multiple playback heads in respective channels, wherein the blocks of data include a selected number of television lines corresponding to each pass of the heads, and wherein overlap in time may occur between successive blocks of data being recovered via respective channels, comprising: a first memory unit for storing a first data block in a first channel; a second memory unit for storing a second data block in a second channel; a first selector control circuit coupled to the first memory unit for loading the first data block in response to its timing signal; a second selector control circuit coupled to the second memory unit for loading the second data block in response to its timing signal; said first and second selector control circuits including respective first and second circuit means for determining any overlap between the first and second stored data blocks; and data selector means coupled to the first and second memory units for selecting respective data blocks alternately from the channels one at a time in response to the determined overlap by the first and second circuit means.

Claim 19

The circuit of claim 15 including: first and second pass counter circuits coupled to the respective first and second circuit means for supplying first and second activate signals indicative of the number of television lines in each pass of the heads; and said first and second circuit means include first and second write-to-read transfer circuits coupled to respective first and second pass counter circuits and responsive to the activate signals and the data block timing signals for supplying a data block read signal to the corresponding memory unit and an associated data select signal to the data selector means.

Claim 20

The circuit of claim 16 further including: first and second read stop circuits coupled to respective first and second pass counter circuits and to first and second write-to-read transfer circuits for supplying respective first and second last line hold-off signals to the second and first memory units respectively, for inhibiting reading by the second memory unit until read out of the first memory unit is finished, and vice versa.

Claim 23

The method of claim 18 including: determining the time period of each of the successively stored data blocks; and delaying the reading out of the second stored data block in response to the determined time period of the previously stored data block.