Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
297 words
A digital-to-analog converter circuit, comprising: a current switch including a plurality of differential amplifies, each differential amplifier including a pair of emitter-coupled NPN transistors, a binary-weighted NPN transistor constant-current source including a current source transistor having a base terminal and a binary-weighted emitter resistor, an input for receiving a complementary logic input voltage signal and an output for developing a binary-weighted output current corresponding to the complementary logic input voltage signal, wherein the maximum output current has a value of I MAX ; a pair of load impedances each having a value of R L for receiving the total binary-weighted output current and for developing a complementary output voltage; and a current reference source including a source of constant reference current having a value of I R , an operational amplifier having a positive input, a negative input, and an output, the positive input being coupled to the source of constant reference current, the negative input being coupled to ground, a first transistor having a base, a collector, and an emitter, the collector being coupled to the positive input through an impedance element having a value of R L I MAX /I R , the base being coupled to a reference voltage, and a second transistor having a base, a collector, and an emitter, the collector being coupled to the emitter of the first transistor, the emitter being coupled to a supply voltage, and the base being coupled to the output of the operational amplifier and to the base terminal of each of the current source transistors, the value of the impedance element being selected to compensate for the effect of the Early voltages of the emitter-coupled NPN transistors, thereby substantially eliminating the sensitivity of the output current and corresponding output voltage to fluctuations in Early voltage.
Claim 2
Dependent Claim
297 words
A digital-to-analog converter circuit, comprising: a current switch including a plurality of differential amplifies, each differential amplifier including a pair of emitter-coupled NPN transistors, a binary-weighted NPN transistor constant-current source including a current source transistor having a base terminal and a binary-weighted emitter resistor, an input for receiving a complementary logic input voltage signal and an output for developing a binary-weighted output current corresponding to the complementary logic input voltage signal, wherein the maximum output current has a value of I MAX ; a pair of load impedances each having a value of R L for receiving the total binary-weighted output current and for developing a complementary output voltage; and a current reference source including a source of constant reference current having a value of I R , an operational amplifier having a positive input, a negative input, and an output, the positive input being coupled to the source of constant reference current, the negative input being coupled to ground, a first transistor having a base, a collector, and an emitter, the collector being coupled to the positive input through an impedance element having a value of R L I MAX /I R , the base being coupled to a reference voltage, and a second transistor having a base, a collector, and an emitter, the collector being coupled to the emitter of the first transistor, the emitter being coupled to a supply voltage, and the base being coupled to the output of the operational amplifier and to the base terminal of each of the current source transistors, the value of the impedance element being selected to compensate for the effect of the Early voltages of the emitter-coupled NPN transistors, thereby substantially eliminating the sensitivity of the output current and corresponding output voltage to fluctuations in Early voltage.
Claim 3
Dependent Claim
30 words
A circuit as in claim 1 wherein the value of the reference voltage coupled to the base of the first transistor is substantially equal to a logic 1 voltage level.
Claim 4
Dependent Claim
28 words
A circuit as in claim 1 wherein the emitter areas of the current source transistors are binarily scaled such that the emitter voltage of each transistor is equal.