Load current detecting device for pulse width modulation inverter

Claim 2

A current detecting device for a PWM inverter including a plurality of arms connected in parallel with a d.c. power source and each including a series connection of two switching elements, a.c. output terminals each being provided by the connection point between the two switching elements constituting each of said arms, and a PWM switching control circuit continuously and alternately applying a plurality of switching control signals to one and the other of said two switching elements constituting each of said arms respectively, said current detecting device comprising: shunt resistors connected between said d.c. power source and one of said two switching elements constituting each of said arms respectively; and sample-hold means associated with said shunt resistors connected in series with one of said switching elements belonging to the associated arms respectively, each of said sample-hold means providing output signals corresponding to output currents of said a.c. output terminals by sampling and holding a voltage appearing across the associated shunt resistor at specific timing in a conduction period of said switching element belonging to the associated arm.

Claim 3

A current detecting device for a PWM inverter including three arms connected in parallel with a d.c. power source and each including a series connection of two switching elements, a.c. output terminals each being provided by the connection point between the two switching elements constituting each of said arms, and a PWM switching control circuit continuously and alternately applying a plurality of switching control signals to one and the other of said two switching elements constituting each of said arms respectively, said current detecting device comprising: two shunt resistors connected between said d.c. power source and one of said switching elements constituting each of the two arms among said three arms respectively; two sample-hold means associated with said shunt resistors connected in series with one of said switching elements belonging to the associated arms respectively, each of said sample-hold means for providing output signals corresponding to output currents of a.c. output terminals of said two arms by sampling and holding a voltage appearing across the associated shunt resistor at specific timing in a conduction period of said switching element belonging to the associated arm; and vector computing means for computing on the basis of said output signals from said two sample-hold means, a value by multiplying the sum of vector outputs of said two sample-hold means by -1.

Claim 4

A current detecting device for a PWM inverter including three arms connected in parallel with a d.c. power source and each including a series connection of two switching elements, a.c. output terminals each being provided by the connection point between the two switching elements constituting each of said arms, and a PWM switching control circuit continuously and alternately applying a plurality of switching control signals to one and the other of said two switching elements constituting each of said arms respectively, said current detecting device comprising: two shunt resistors connected between said d.c. power source and one of said switching elements constituting each of the two arms among said three arms respectively; two sample-hold means associated with said shunt resistors connected in series with one of said switching elements belonging to the associated arms respectively, each of said sample-hold means for providing output signals corresponding to output currents of a.c. output terminals of said two arms by sampling and holding a voltage appearing across the associated shunt resistor at specific timing in a conduction period of said switching element belonging to the associated arm; and vector computing means for computing on the basis of said output signals from said two sample-hold means, a value by multiplying the sum of vector outputs of said two sample-hold means by -1.

Claim 5

A current detecting device for a PWM inverter including a plurality of arms connected in parallel with a d.c. power source and each including a series connection of an upper arm and a lower arm each having a switching element, a.c. output terminals each being provided by the connection point between said upper and lower arms constituting each of said arms respectively, and a PWM switching control circuit continuously and alternately applying a plurality of switching control signals to said upper and lower arms constituting each of arms respectively, said current detecting device comprising: shunt resistors connected between a minus terminal of said d.c. power source and said lower arms respectively; and sample-hold means associated with said shunt resistors connected in series with said lower arms belonging to the associated arms respectively, each of said sample-hold means providing output signals corresponding to output currents of said a.c. output terminals by sampling and holding a voltage appearing across the associated shunt resistor at specific timing in a conduction period of said lower arm.

Claim 6

A current detecting device for a PWM inverter including a plurality of arms connected in parallel with a d.c. power source and each including a series connection of an upper arm and a lower arm each having a switching element, a.c. output terminals each being provided by the connection point between said upper and lower arms constituting each of said arms respectively, and a PWM switching control circuit continuously and alternately applying a plurality of switching control signals to said upper and lower arms constituting each of arms respectively, said current detecting device comprising: shunt resistors connected between a minus terminal of said d.c. power source and said lower arms respectively; and sample-hold means associated with said shunt resistors connected in series with said lower arms belonging to the associated arms respectively, each of said sample-hold means providing output signals corresponding to output currents of said a.c. output terminals by sampling and holding a voltage appearing across the associated shunt resistor at specific timing in a conduction period of said lower arm.

Claim 7

A current detecting device for a PWM inverter including a plurality of arms connected in parallel with a d.c. power source and each including a series connection of an upper arm and a lower arm each having a switching element, a.c. output terminals each being provided by the connection point between said upper and lower arms constituting each of said arms respectively, and a PWM switching control circuit continuously and alternately applying a plurality of switching control signals to one and the other of said switching elements constituting each of said arms respectively, said current detecting device comprising: shunt resistors connected between said d.c. power source and one of said switching elements constituting each of said arms respectively; and extrapolating means for providing output signals corresponding to output currents of said a.c. output terminals by estimating, through extrapolation, the voltage values which will be held next by said sample-hold means on the basis of time-series data of voltages appearing across said shunt resistors and held by said sample-hold means in the past respectively.

Claim 8

A current detecting device for a PWM inverter including a plurality of arms connected in parallel with a d.c. power source and each including a series connection of an upper arm and a lower arm each having a switching element, a.c. output terminals each being provided by the connection point between said upper and lower arms constituting each of said arms respectively, and a PWM switching control circuit continuously and alternately applying a plurality of switching control signals to one and the other of said switching elements constituting each of said arms respectively, said current detecting device comprising: shunt resistors connected between said d.c. power source and one of said switching elements constituting each of said arms respectively; and extrapolating means for providing output signals corresponding to output currents of said a.c. output terminals by estimating, through extrapolation, the voltage values which will be held next by said sample-hold means on the basis of time-series data of voltages appearing across said shunt resistors and held by said sample-hold means in the past respectively.

Claim 9

A PWM inverter including a plurality of arms connected in parallel with a d.c. power source and each including a series connection of an upper arm and a lower arm each having a switching element, a.c. output terminals each being provided by the connection point between said upper and lower arms constituting each of said arms respectively, and means for continuously and alternately applying a plurality of switching control signals to said upper and lower arms constituting each of said arms respectively, said PWM inverter comprising: waveform command generating means generating command signals commanding current waveforms to be supplied from said a.c. output terminals; carrier wave generating means generating a carrier wave signal; shunt resistors connected between said d.c. power source and one of said switching elements constituting each of said arms respectively; sample-hold means associated with said shunt resistors connected in series with one of said switching elements belonging to the associated arms respectively, each of said sample-hold means sampling and holding a voltage appearing across the associated shunt resistor in synchronism with the output of said carrier wave generating means and at specific timing in a conduction period of said switching element belonging to the associated arm; difference computing means computing differences between the outputs of said waveform command generating means and the outputs of said sample-hold means respectively; and switching control means comparing the outputs of said difference computing means with the output of said carrier wave generating means to produce said switching control signals for switching said switching elements.

Claim 10

A PWM inverter including a plurality of arms connected in parallel with a d.c. power source and each including a series connection of an upper arm and a lower arm each having a switching element, a.c. output terminals each being provided by the connection point between said upper and lower arms constituting each of said arms respectively, and means for continuously and alternately applying a plurality of switching control signals to said upper and lower arms constituting each of said arms respectively, said PWM inverter comprising: waveform command generating means generating command signals commanding current waveforms to be supplied from said a.c. output terminals; carrier wave generating means generating a carrier wave signal; shunt resistors connected between said d.c. power source and one of said switching elements constituting each of said arms respectively; sample-hold means associated with said shunt resistors connected in series with one of said switching elements belonging to the associated arms respectively, each of said sample-hold means sampling and holding a voltage appearing across the associated shunt resistor in synchronism with the output of said carrier wave generating means and at specific timing in a conduction period of said switching element belonging to the associated arm; difference computing means computing differences between the outputs of said waveform command generating means and the outputs of said sample-hold means respectively; and switching control means comparing the outputs of said difference computing means with the output of said carrier wave generating means to produce said switching control signals for switching said switching elements.

Claim 11

A PWM inverter according to claim 5, wherein said sample-hold means have associated therewith reference signal generating means generating a signal representative of a reference level and comparing means comparing the output of said carrier wave generating means with the output of said reference signal generating means, and each of said sample-hold means samples and holds the terminal voltage of said shunt resistor when the output of said carrier wave generating means becomes larger than the output of said reference signal generating means.

Claim 12

A PWM inverter according to claim 5, wherein said sample-hold means have associated therewith reference signal generating means generating a signal representative of a reference level and comparing means comparing the output of said carrier wave generating means with the output of said reference signal generating means, and each of said sample-hold means samples and holds the terminal voltage of said shunt resistor when the output of said carrier wave generating means becomes smaller than the output of said reference signal generating means.

Claim 13

A PWM inverter according to claim 5, wherein said sample-hold means have associated therewith reference signal generating means generating a signal representative of a reference level and comparing means comparing the output of said carrier wave generating means with the output of said reference signal generating means, and each of said sample-hold means samples and holds the terminal voltage of said shunt resistor when the absolute value of the output of said carrier wave generating means becomes larger than the output of said reference signal generating means.

Claim 14

A PWM inverter according to claim 5, wherein each of said sample-hold means includes a field effect transistor and a capacitor.

Claim 15

A PWM inverter including a plurality of arms connected in parallel with a d.c. power source and each including a series connection of an upper arm and a lower arm each having a switching element, a.c. output terminals each being provided by the connection point between said two switching elements constituting each of said arms respectively, and means for continuously and alternately applying a plurality of switching control signals to said upper and lower arms constituting each of said arms respectively, said PWM inverter comprising: waveform command data generating means generating data representative of current waveforms to be supplied from said a.c. output terminals; carrier wave data generating means generating data representative of carrier wave at a predetermined time interval; shunt resistors connected between said d.c. power source and one of said two switching elements constituting each of said arms respectively; sample-hold means associated with said shunt resistors connected in series with one of said switching elements belonging to the associated arms respectively, each of said sample-hold means sampling and holding a voltage appearing across the associated shunt resistor in synchronism with the period of said carrier wave data generated from said carrier wave data generating means and at specific timing in a conduction period of said switching element belonging to the associated arm; difference computing means computing differences between the outputs of said waveform command data generating means and the outputs of said sample-hold means respectively; and switching control means comparing the outputs of said difference computing means with the output of said carrier wave data generating means to produce said switching control signals for switching said switching elements.

Claim 16

A PWM inverter including a plurality of arms connected in parallel with a d.c. power source and each including a series connection of an upper arm and a lower arm each having a switching element, a.c. output terminals each being provided by the connection point between said two switching elements constituting each of said arms respectively, and means for continuously and alternately applying a plurality of switching control signals to said upper and lower arms constituting each of said arms respectively, said PWM inverter comprising: waveform command data generating means generating data representative of current waveforms to be supplied from said a.c. output terminals; carrier wave data generating means generating data representative of carrier wave at a predetermined time interval; shunt resistors connected between said d.c. power source and one of said two switching elements constituting each of said arms respectively; sample-hold means associated with said shunt resistors connected in series with one of said switching elements belonging to the associated arms respectively, each of said sample-hold means sampling and holding a voltage appearing across the associated shunt resistor in synchronism with the period of said carrier wave data generated from said carrier wave data generating means and at specific timing in a conduction period of said switching element belonging to the associated arm; difference computing means computing differences between the outputs of said waveform command data generating means and the outputs of said sample-hold means respectively; and switching control means comparing the outputs of said difference computing means with the output of said carrier wave data generating means to produce said switching control signals for switching said switching elements.

Claim 17

A PWM inverter according to claim 10, wherein said sample-hold means have associated therewith reference data generating means generating data of a reference level and comparing means comparing the output of said carrier wave data generating means with the output of said reference data generating means, and each of said sample-hold means samples and holds the terminal voltage of said shunt resistor when the output of said carrier wave data generating means becomes smaller than the output of said reference data generating means.

Claim 18

A PWM inverter according to claim 10, wherein said sample-hold means have associated therewith reference data generating means generating data of a reference level and comparing means comparing the output of said carrier wave data generating means with the output of said reference data generating means, and each of said sample-hold means samples and holds the terminal voltage of said shunt resistor when the absolute value of the output of said carrier wave generating means becomes larger than the output of said reference data generating means.

Claim 19

A PWM inverter according to claim 10, wherein said sample-hold means have associated therewith reference data generating means generating data of a reference level and comparing means comparing the output of said carrier wave data generating means with the output of said reference data generating means, and each of said sample-hold means samples and holds the terminal voltage of said shunt resistor when the output of said carrier wave data generating means becomes larger than the output of said reference data generating means.

Claim 20

A PWM inverter including three arms connected in parallel with a d.c. power source and each including a series connection of an upper arm and a lower arm each having a switching element, a.c. output terminals each being provided by the connection point between said two switching elements constituting each of said arms respectively, and means for continuously and alternately applying a plurality of switching control signals to one and the other of said two switching elements constituting each of said arms respectively, said PWM inverter comprising: waveform command data generating means generating data representative of current waveforms to be supplied from said a.c. output terminals; carrier wave data generating means generating data representative of carrier wave at a predetermined time interval; two shunt resistors connected between said d.c. power source and one of said two switching elements constituting each of the two arms among said three arms respectively; two sample-hold means associated with said shunt resistors connected in series with one of said switching elements belonging to the associated arms respectively, each of said sample-hold means sampling and holding a voltage appearing across the associated shunt resistor in synchronism with the period of the carrier wave data generated from said carrier wave data generating means and at specific timing in a conduction period of said switching element belonging to the associated arm; vector computing means computing a value obtained by multiplying the sum of vector outputs of said two sample-hold means by -1; difference computing means computing differences between the two outputs of said waveform command data generating means and the outputs of said sample-hold means and between the remaining output of said waveform command data generating means and the output of said vector computing means respectively; and switching control means comparing the outputs of said difference computing means with the output of said carrier wave data generating means to produce said switching control signals for switching said switching elements.

Claim 21

A PWM inverter including three arms connected in parallel with a d.c. power source and each including a series connection of an upper arm and a lower arm each having a switching element, a.c. output terminals each being provided by the connection point between said two switching elements constituting each of said arms respectively, and means for continuously and alternately applying a plurality of switching control signals to one and the other of said two switching elements constituting each of said arms respectively, said PWM inverter comprising: waveform command data generating means generating data representative of current waveforms to be supplied from said a.c. output terminals; carrier wave data generating means generating data representative of carrier wave at a predetermined time interval; two shunt resistors connected between said d.c. power source and one of said two switching elements constituting each of the two arms among said three arms respectively; two sample-hold means associated with said shunt resistors connected in series with one of said switching elements belonging to the associated arms respectively, each of said sample-hold means sampling and holding a voltage appearing across the associated shunt resistor in synchronism with the period of the carrier wave data generated from said carrier wave data generating means and at specific timing in a conduction period of said switching element belonging to the associated arm; vector computing means computing a value obtained by multiplying the sum of vector outputs of said two sample-hold means by -1; difference computing means computing differences between the two outputs of said waveform command data generating means and the outputs of said sample-hold means and between the remaining output of said waveform command data generating means and the output of said vector computing means respectively; and switching control means comparing the outputs of said difference computing means with the output of said carrier wave data generating means to produce said switching control signals for switching said switching elements.

Claim 22

A PWM inverter according to claim 14, wherein said shunt resistors are connected between a minus terminal of said d.c. power source and said lower arms respectively.

Claim 23

A PWM inverter including three arms connected in parallel with a d.c. power source and each including a series connection of an upper arm and a lower arm each having a switching element, a.c. output terminals each being provided by the connection point between said two switching elements constituting each of said arms respectively, and means for continuously and alternately applying a plurality of switching control signals to one and the other of said two switching elements constituting each of said arms respectively, said PWM inverter comprising: waveform command data generating means generating data representative of current waveforms to be supplied from said a.c. output terminals; carrier wave data generating means generating data representative of carrier wave at a predetermined time interval; two shunt resistors connected between said d.c. power source and one of said two switching elements constituting each of the two arms among said three arms respectively; two sample-hold means associated with said shunt resistors connected in series with one of said switching elements belonging to the associated arms respectively, each of said sample-hold means sampling and holding a voltage appearing across the associated shunt resistor in synchronism with the period of the carrier wave data generated from said carrier wave data generating means and at specific timing in a conduction period of said switching element belonging to the associated arm; vector computing means computing a value obtained by multiplying the sum of vector outputs of said two sample-hold means by -1; extrapolating means estimating, by extrapolation, the values which will be held next by said sample-hold means on the basis of time-series data of voltages appearing across said shunt resistors and held by said sample-hold means in the past respectively; difference computing means computing differences between the outputs of said extrapolating means and the outputs of said sample-hold means respectively; and switching control means comparing the outputs of said difference computing means with the output of said carrier wave data generating means to produce said switching control signals for switching said switching elements.

Claim 24

A PWM inverter including three arms connected in parallel with a d.c. power source and each including a series connection of an upper arm and a lower arm each having a switching element, a.c. output terminals each being provided by the connection point between said two switching elements constituting each of said arms respectively, and means for continuously and alternately applying a plurality of switching control signals to one and the other of said two switching elements constituting each of said arms respectively, said PWM inverter comprising: waveform command data generating means generating data representative of current waveforms to be supplied from said a.c. output terminals; carrier wave data generating means generating data representative of carrier wave at a predetermined time interval; two shunt resistors connected between said d.c. power source and one of said two switching elements constituting each of the two arms among said three arms respectively; two sample-hold means associated with said shunt resistors connected in series with one of said switching elements belonging to the associated arms respectively, each of said sample-hold means sampling and holding a voltage appearing across the associated shunt resistor in synchronism with the period of the carrier wave data generated from said carrier wave data generating means and at specific timing in a conduction period of said switching element belonging to the associated arm; vector computing means computing a value obtained by multiplying the sum of vector outputs of said two sample-hold means by -1; extrapolating means estimating, by extrapolation, the values which will be held next by said sample-hold means on the basis of time-series data of voltages appearing across said shunt resistors and held by said sample-hold means in the past respectively; difference computing means computing differences between the outputs of said extrapolating means and the outputs of said sample-hold means respectively; and switching control means comparing the outputs of said difference computing means with the output of said carrier wave data generating means to produce said switching control signals for switching said switching elements.