US4772852A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase-frequency comparator for phase-locked loops
Assignee: Siemens Telecomunicazioni SpA
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Filing: 1986-11-06
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Granted: 1988-09-20
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Expires: 2006-11-06
Abstract
Abstract An instantaneous comparison unit with an associated sequential state logic circuit is described which functions to maintain a condition of phase locking with a reference signal which is substantially immune to disturbances which cause losses or additions of signal fronts. Continuous phase shifting conditions during the transient, which precedes phase locking, is detected and compensated for by the disclosed circuit.
Inventors
- 👤 Maurizio Viti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:47
CPC Classifications
G; G01; G01R; G01R25/00; G01R25/08; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/10
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
166 words
A phase-frequency comparator for phase-locked loops comprising: means for providing an instantaneous phase comparison by periodically detecting the phase difference between a reference signal and a comparison signal and including means for producing at each detection an output signal representative of said detected phase difference and an additional output signal representative of a correction signal; a sequential state logic circuit means for detecting the magnitude and the correction sign of said detected phase difference and for deriving and storing data representative of the magnitude and phase difference correction sign information; and a selection logic means controlled by said sequential state logic circuit means for generating a correction signal having a constant sign, and including means for cancelling out the detected phase difference when said detected phase difference is greater than a predetermined value; and means for deriving a correction signal, whereby said correction signal sign is a function of the output of said comparison unit only when said phase difference is less than said predetermined value.
Claim 2
Dependent Claim
166 words
A phase-frequency comparator for phase-locked loops comprising: means for providing an instantaneous phase comparison by periodically detecting the phase difference between a reference signal and a comparison signal and including means for producing at each detection an output signal representative of said detected phase difference and an additional output signal representative of a correction signal; a sequential state logic circuit means for detecting the magnitude and the correction sign of said detected phase difference and for deriving and storing data representative of the magnitude and phase difference correction sign information; and a selection logic means controlled by said sequential state logic circuit means for generating a correction signal having a constant sign, and including means for cancelling out the detected phase difference when said detected phase difference is greater than a predetermined value; and means for deriving a correction signal, whereby said correction signal sign is a function of the output of said comparison unit only when said phase difference is less than said predetermined value.
Claim 3
Dependent Claim
16 words
A comparator in accordance with claim 1 wherein said comparator includes a plurality of flip-flop circuits.
Claim 4
Dependent Claim
68 words
A comparator in accordance with claim 1 wherein said sequential state logic circuit means includes a physical state detection circuit operating at a frequency which is a multiple of said comparison signal frequency for periodically sampling the phase difference to detect one of four physical states corresponding to phase differences falling between -π and -π/2, between -π/2 and 0, between 0 and +π/2 and between +π/2 and +π.
Claim 5
Dependent Claim
31 words
A comparator in accordance with claim 3 wherein said physical state detection circuit includes a sampling flip-flop having as an input a detected phase difference signal from said comparison circuit output.
Claim 6
Dependent Claim
24 words
A comparator in accordance with claim 3 wherein said storage circuit of said physical logic state circuit is comprised of a plurality of flip-flops.
Claim 7
Dependent Claim
38 words
A comparator in accordance with claim 3 wherein said sequential state logic circuit includes means for updating of a present logic state storage circuit only when the physical state detected is stored for a predetermined period of time.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-20 | 1992-03-21 | 1992-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-20 | 1996-03-21 | 1996-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-20 | 2000-03-21 | 2000-09-20 | $7700.00 | Window Closed / Lapsed |