Method and apparatus for phase reference recovery in high speed fast turnaround modem

Claim 2

In a data communications receiver, of the type comprising a data decoder and a phase locked loop comprising a loop filter, for receiving and decoding data encoded in a received baseband signal using a signal constellation consisting of a plurality of discrete points, each of said discrete points having a particular amplitude and a particular phase relative to a predetermined reference phase; an improved phase reference recovery circuit for detecting said predetermined reference phase in said received signal, comprising in combination: a first constellation decision circuit for providing a first detected data signal and a first magnitude error signal in response to said received baseband signal; phase shifting means for providing a shifted baseband signal in response to said received baseband signal, said shifted baseband signal having a phase which differs from the phase of said received baseband signal by a predetermined phase increment; a second constellation decision circuit for providing a second detected data signal and a second magnitude error signal in response to said shifted baseband signal; means for providing an angular error signal in response to a selected one of said received baseband signal and said shifted baseband signal; means for providing said angular error signal to said loop filter; comparator means for comparing said first and second magnitude error signals and for providing a selection signal in response to the relative values of said first and second magnitude error signals; and selection means connected to said comparator means and to said first and second constellation decision circuits for providing one of said first and second detected data signals to said data decoder in response to said selection signal.

Claim 3

A data communications receiver as recited in claim 1 wherein: said comparator means comprises first and second low pass filters for low pass filtering said first and second magnitude error signals, respectively, to provide respective first and second filtered magnitude error signals; and said comparator means provides said selection signal in response to the relative values of said first and second filtered magnitude error signals.

Claim 4

A data communications receiver as recited in claim 2 wherein: each of said first and second low pass filters is a finite impulse response digital filter having a transfer function of ##EQU3## wherein n is an integer greater than zero.

Claim 5

A data communications receiver as recited in claim 3 wherein: said integer n=5.

Claim 6

A data communications receiver as recited in claim 1 wherein: said comparator means comprises an algebraic summing junction for providing an algebraic sum of said first and second magnitude error signals to provide a magnitude error difference signal; a low pass filter for low pass filtering said magnitude error difference signal to provide a filtered magnitude error difference signal; and said comparator means provides said selection signal in response to said filtered magnitude error difference signal being greater than a predetermined threshold value.

Claim 7

A data communications receiver as recited in claim 5 wherein: said pass filter is a finite impulse response digital filter having a transfer function of ##EQU4## wherein n is an integer greater than zero.

Claim 8

A data communications receiver as recited in claim 6 wherein: said integer n=5.

Claim 9

In a data communications receiver, of the type comprising a data decoder, a complex adaptive equalizer for providing an equalized baseband data signal in response to a received baseband data signal, and a phase locked loop comprising a loop filter, for receiving and decoding data encoded in said received baseband signal using a signal constellation consisting of a plurality of discrete points, each of said discrete points having a particular amplitude and a particular phase relative to a predetermined reference phase; an improved phase reference recovery circuit for detecting said predetermined reference phase in said received signal, comprising in combination: a first constellation decision circuit for providing a first detected data signal and a first complex error signal in response to said equalized baseband signal; phase shifting means for providing a shifted baseband signal in response to said equalized baseband signal, said shifted baseband signal having a phase which differs from the phase of said equalized baseband signal by a predetermined phase increment; a second constellation decision circuit for providing a second detected data signal and a second complex error signal in response to said shifted baseband signal; means for providing an angular error signal in response to a selected one of said received baseband signal and said shifted baseband signal; means for providing said angular error signal to said loop filter; means for providing a first magnitude error signal in response to said first complex error signal and a second magnitude error signal in response to said second complex error signal; comparator means for comparing said first and second magnitude error signals and for providing a selection signal in response to the relative values of said first and second magnitude error signals; and selection means connected to said comparator means and to said first and second constellation decision circuits for providing one of said first and second detected data signals to said data decoder and one of said first and second complex error signals to said adaptive equalizer in response to said selection signal.

Claim 10

In a data communications receiver, of the type comprising a data decoder, a complex adaptive equalizer for providing an equalized baseband data signal in response to a received baseband data signal, and a phase locked loop comprising a loop filter, for receiving and decoding data encoded in said received baseband signal using a signal constellation consisting of a plurality of discrete points, each of said discrete points having a particular amplitude and a particular phase relative to a predetermined reference phase; an improved phase reference recovery circuit for detecting said predetermined reference phase in said received signal, comprising in combination: a first constellation decision circuit for providing a first detected data signal and a first complex error signal in response to said equalized baseband signal; phase shifting means for providing a shifted baseband signal in response to said equalized baseband signal, said shifted baseband signal having a phase which differs from the phase of said equalized baseband signal by a predetermined phase increment; a second constellation decision circuit for providing a second detected data signal and a second complex error signal in response to said shifted baseband signal; means for providing an angular error signal in response to a selected one of said received baseband signal and said shifted baseband signal; means for providing said angular error signal to said loop filter; means for providing a first magnitude error signal in response to said first complex error signal and a second magnitude error signal in response to said second complex error signal; comparator means for comparing said first and second magnitude error signals and for providing a selection signal in response to the relative values of said first and second magnitude error signals; and selection means connected to said comparator means and to said first and second constellation decision circuits for providing one of said first and second detected data signals to said data decoder and one of said first and second complex error signals to said adaptive equalizer in response to said selection signal.

Claim 11

A data communications receiver as recited in claim 8 wherein: said comparator means comprises first and second low pass filters for low pass filtering said first and second magnitude error signals, respectively, to provide respective first and second filtered magnitude error signals; and said comparator means provides said selection signal in response to the relative values of said first and second filtered magnitude error signals.

Claim 12

A data communications receiver as recited in claim 9 wherein: each of said first and second low pass filters is a finite impulse response digital filter having a transfer function of ##EQU5## wherein n is an integer greater than zero.

Claim 13

A data communications receiver as recited in claim 10 wherein: said integer n=5.

Claim 14

A data communications receiver as recited in claim 8 wherein: said comparator means comprises an algebraic summing junction for providing an algebraic sum of said first and second magnitude error signals to provide a magnitude error difference signal; a low pass filter for low pass filtering said magnitude error difference signal to provide a filtered magnitude error difference signal; and said comparator means provides said selection signal in response to said filtered magnitude error difference signal being greater than a predetermined threshold value.

Claim 15

A data communications receiver as recited in claim 12 wherein: said pass filter is a finite impulse response digital filter having a transfer function of ##EQU6## wherein n is an integer greater than zero.

Claim 16

A data communications receiver as recited in claim 13 wherein: said integer n=5.

Claim 19

A method of locking a data communications receiver onto a predetermined reference phase as recited in claim 15 wherein: said step of comparing said first and second magnitude error signals includes a step of low pass filtering said first and second magnitude error signals.

Claim 20

A method of locking a data communications receiver onto a predetermined reference phase as recited in claim 15 wherein said step of comparing said first and second magnitude error signals includes the steps of: providing a difference signal in response a difference of said first and second magnitude error signals; and low pass filtering said difference signal.

Claim 21

A method of locking a data communications receiver onto a predetermined reference phase as recited in claim 15 wherein: said step of comparing said first and second magnitude error signals includes a step of averaging said first and second magnitude error signals over a predetermined number of signal times of said received phase modulated signal.

Claim 22

A method of locking a data communications receiver onto a predetermined reference phase as recited in claim 15 wherein said step of comparing said first and second magnitude error signals includes the steps of: providing a difference signal in response a difference of said first and second magnitude error signals; and averaging said difference signal over a predetermined number of signal times of said received phase modulated signal.