Virtual vector registers for vector processing system

Claim 1

In a data processing system comprising a main store; a processing unit; a working store comprising a pair of buffer stores connected between said main store and said processing unit, each of said buffer stores having a multiplicity of consecutively addressed storage locations, one buffer store having a storage location whose address is next to the address of a storage location in the other buffer store; and a data transfer controller connected to said main store and said buffer stores; said processing unit and said data transfer controller selectively operating to concurrently transfer vector operands between one of said buffer stores and said processing unit and between the other of said buffer stores and said main store, means for processing vector operands having a number of vector elements to perform both storage-to-storage (SS) vector operations and register-to-register (RR) vector operations, said means comprising: program store means for storing a user's program including SS instructions defining SS vector operations and RR instructions defining RR vector operations, said program including at least one RR instruction specifying the number of vector elements in a first vector operand, said one RR instruction further specifying a source vector register for storing said first vector operand, said one RR instruction further specifying a destination vector register for receiving a second vector operand resulting from the RR operation defined by said one RR instruction, said vector registers being located in said buffer stores whereby one of said first and second vector operands extends across and is stored in consecutively addressed storage locations in both of said buffer stores; and control means, including said data transfer controller, connected to said main store, said processing unit and said buffer stores, said control means being responsive to a first SS instruction to automatically perform the serial operations of inputting a third vector operand from said main store into one of said buffer stores at predetermined locations therein, transferring said third vector operand from said one buffer store into said processing unit for processing, outputting a fourth vector operand from said processing unit into said one buffer store at predetermined locations therein, and outputting said fourth vector operand from said one buffer store into said main store; said control means being further responsive to said one RR instruction to automatically input said first vector operand one vector element at a time from said source vector register into said processing unit and then outputting said second vector operand one vector element at a time from said processing unit into said destination vector register whereby both of said buffer stores are accessed while executing said one RR instruction.