Computer interface unit for an audiometer

Claim 2

A computer interface unit for an audiometer having a plurality of controllable audiometer modules, said interface unit permitting control of said audiometer modules by means of a computer and comprising: (a) a plurality of first control lines, including both input and output lines, there being a plurality of input lines and at least one output line, the first lines being connectable to a computer and each first line having a d-c isolating coupler therein; (b) a plurality of decoders connected to said first lines; (c) a plurality of memories, each connected to one of said decoders; (d) a plurality of second control lines connecting said memories with said audiometer modules, whereby said audiometer modules may be controlled by said computer; (e) a NAND gate connected through inverters to individual ones of said input lines and without inverters to other individual ones of said input lines, said NAND gate having an output line connected via an integrator and at least one Schmitt trigger circuit to an associated one of said memories; and (f) an OR gate having an input connected to the line between said Schmitt triggers and an output connected to said one output line for providing a reply signal to said computer.

Claim 3

The interface unit defined in claim 1, further comprising a mono-stable multi-vibrator having an input connected to said line between said Schmitt triggers for producing an output control signal for interference blanking during a prescribed period.

Claim 4

The interface unit defined in claim 2, wherein said prescribed period is in the range of 20 MS to 0.2 seconds.

Claim 5

A computer interface unit for an audiometer having a plurality of controllable audiometer modules, said interface unit permitting control of said audiometer modules by means of a computer and comprising: (a) a plurality of first control lines including both input and output lines, connectable to a computer, each first line having a d-c isolating coupler therein; (b) a plurality of decoders connected to said first lines; (c) a plurality of memories, each connected to one of said decoders; (d) a plurality of second control lines connecting said memories with said audiometer modules, whereby said audiometer modules may be controlled by said computer; (e) an OR gate, having plural inputs and a single output; (f) a plurality of reply lines interconnecting said decoders with the respective inputs of said OR gate, the output of said OR gate being connected to said output line which has a d-c isolating coupler therein; (g) a second memory for storing a bit pattern, said memory having a plurality of outputs for presenting signals representing said bit pattern; and (h) a plurality of AND gates, each having inputs connected to one of said memory outputs and to one of said reply lines connected to a decoder, said AND gates each having an output connected to said OR gate.

Claim 6

A computer interface unit for an audiometer having a plurality of controllable audiometer modules, said interface unit permitting control of said audiometer modules by means of a computer and comprising: (a) a plurality of first control lines including both input and output lines, connectable to a computer, each first line having a d-c isolating coupler therein; (b) a plurality of decoders connected to said first lines; (c) a plurality of memories, each connected to one of said decoders; (d) a plurality of second control lines connecting said memories with said audiometer modules, whereby said audiometer modules may be controlled by said computer; (e) an OR gate, having plural inputs and a single output; (f) a plurality of reply lines interconnecting said decoders with the respective inputs of said OR gate, the output of said OR gate being connected to said output line which has a d-c isolating coupler therein; (g) a second memory for storing a bit pattern, said memory having a plurality of outputs for presenting signals representing said bit pattern; and (h) a plurality of AND gates, each having inputs connected to one of said memory outputs and to one of said reply lines connected to a decoder, said AND gates each having an output connected to said OR gate.

Claim 7

A computer interface unit for an audiometer having a plurality of controllable audiometer modules, said interface unit permitting control of said audiometer modules by means of a computer and comprising: (a) a plurality of first control lines, connectable to a computer, each first line having a d-c isolating coupler therein; (b) a plurality of decoders connected to said first lines; (c) a plurality of memories, each connected to one of said decoders; and (d) a plurality of second control lines connecting said memories with said audiometer modules, whereby said audiometer modules may be controlled by said computer, wherein each data word is stored, following an address word and after a preselectable waiting time without a clock signal transmitted from said computer, in a data memory assigned to the respective address of such address word, the waiting time being provided by an integrator connected to receive the output signal of the address decoder, a part of the data words maximally possible through the number of control lines being reserved for addresses; wherein the address decoder is constructed so that it automatically generates a control signal for interference voltage blanking during the command execution, the duration of which is selectable, as well as a reply signal which can switch on a display; and wherein the command memory belonging to an address is prepared for the acceptance of new data and can cause a program branch in said computer.

Claim 8

A computer interface unit for an audiometer having a plurality of controllable audiometer modules, said interface unit permitting control of said audiometer modules by means of a computer and comprising: (a) a plurality of first control lines, connectable to a computer, each first line having a d-c isolating coupler therein; (b) a plurality of decoders connected to said first lines; (c) a plurality of memories, each connected to one of said decoders; and (d) a plurality of second control lines connecting said memories with said audiometer modules, whereby said audiometer modules may be controlled by said computer, wherein each data word is stored, following an address word and after a preselectable waiting time without a clock signal transmitted from said computer, in a data memory assigned to the respective address of such address word, the waiting time being provided by an integrator connected to receive the output signal of the address decoder, a part of the data words maximally possible through the number of control lines being reserved for addresses; wherein the address decoder is constructed so that it automatically generates a control signal for interference voltage blanking during the command execution, the duration of which is selectable, as well as a reply signal which can switch on a display; and wherein the command memory belonging to an address is prepared for the acceptance of new data and can cause a program branch in said computer.

Claim 9

The interface unit defined in claim 5, wherein the direction of signal transmission in a selectable portion of the control lines is reversable either by a computer command or, automatically, after time-out of a time delay element initiated by the respective address decoder, for a selectable period of time.

Claim 10

The interface unit defined in claim 6, wherein said computer controls said audiometer via eight signal lines.

Claim 11

The interface unit defined in claim 5, wherein the reply signals of several address decoders are supplied to said computer via at least one additional reply line by means of an OR circuit.

Claim 12

The interface unit defined in claim 10, wherein only one reply line is used.

Claim 13

The interface unit defined in claim 8, further comprising an address decoder for polling of bit patterns, there being one address decoder for each bit, the reply signal of which is influenced by the state of the associated bit.

Claim 14

The interface unit defined in claim 10, wherein only those bits of the bit pattern which are set bring about a reply signal of the associated address decoders.

Claim 15

The interface unit defined in claim 5, wherein after the disconnection of their address the reply signals for the identification of modules with the same address are transmitted with different delays.

Claim 16

The interface unit defined in claim 5, wherein a reply signal is transmitted only after it has been determined additionally by automatic measuring of the output signals of the modules that the entire audiometer operates satisfactorily, so that in case of error the computer can automatically switch to spare modules.

Claim 17

The interface unit defined in claim 5, wherein a first address and a first data word define a sub-address under which a second data word is stored at a second address.

Claim 18

The interface unit defined in claim 5, wherein to achieve high immunity to interference all control and reply lines are d-c isolated from said computer so that said audiometer modules may be operated with control voltages which differ considerably from those of said computer.

Claim 19

The interface unit defined in claim 15, wherein said d-c isolating couplers are optocouplers which permit differential voltages higher than 4 kV.

Claim 20

The interface unit defined in claim 5, wherein to achieve high immunity to interference all commands are first stored temporarily and then stored permanently only after coincidence, when the address and the data word are repeated.

Claim 21

The interface unit defined in claim 5, wherein an address and a data word are each selected with a separate multi-pole switch and are switched alternately to the bus with a multi-pole reversing switch, and wherein the particular state of the command memory is displayed to the user.

Claim 22

The interface unit defined in claim 5, further comprising (1) hardwired means for permanently providing each address of the address word and a multi-pole switch for selecting a data word; (2) a multi-pole electronic step switch controlled from the off state via the respective command and the address again to the respective command and back to the off state, and (3) means for preventing errors due to simultaneous actuation of several such switches.