Analog to digital converter

Claim 2

An analog to digital converter, comprising; a balanced type integrator having a first input terminal, a second input terminal, a first output terminal and a second output terminal; a comparator having first and second input terminals connected to said first and second output terminals of said integrator; first and second sample capacitors having first ends respectively connected to said first and second input terminals of said integrator; means for applying a difference in an analog input signal between second ends of said first and second sample capacitors in a balanced manner; a counter; first control means responsive to the output of said comparator for controlling said counter, a first internal digital to analog converter responsive to the output of said counter for generating a first internal analog signal; first means for subtracting said first internal analog signal from the charge of said first sample capacitor; a second internal digital to analog converter responsive to the output of said counter for generating a second internal analog signal; second means for subtracting said second internal analog signal from the charge of said second sample capacitor; and third means responsive to the output of said comparator for controlling said counter so as to make the output of said comparator equal to zero.

Claim 3

The analog to digital circuit according to claim 1, in which said third means includes a toggle flip-flop, an exclusive-NOR gate receiving the output of said comparator and an output of said toggle flip-flop, a NOR gate having inputs connected to respective stages of outputs of said counter, an OR gate receiving an output of said NOR gate and an output of said exclusive-NOR gate for controlling said counter, and gate means for inverting the state of said toggle flip-flop.

Claim 4

An analog to digital converter, comprising; a balanced type integrator having a first input terminal, a second input terminal, a first output terminal and a second output terminal; first and second analog signal input terminals; a reference voltage terminal; a ground voltage terminal; first and second capacitor arrays, each of said capacitor arrays including first to n-th (n being a positive integer greater than 2) capacitors having weighted capacitances, the i-th capacitor having a capacitance 2 i-1 ×C (C being constant); first and second feedback capacitors; first and second sample capacitors, a first common line connected to first ends of said first to n-th capacitors of said first capacitor array said first feedback capacitor and said first sample capacitor; a second common line connected to first ends of said first to n-th capacitors of said second capacitor array, said second feedback capacitor and said second sample capacitor; a first switch arrangement including first to n-th switches provided for said first capacitor array, one of said first to n-th switches of said first switch arrangement selectively connecting a second end of one of said first to n-th capacitors of said first capacitor array to one of said reference voltage terminal and said ground voltage terminal; a second switch arrangement including first to n-th switches provided for said second capacitor array, one of said first to n-th switches of said second switch arrangement selectively connecting a second end of one of said first to n-th capacitors of said second capacitor array to one of said reference voltage terminal and said ground voltage terminal; a first feedback switch for selectively connecting a second end of said first feedback capacitor to one of said reference voltage terminal and said ground voltage terminal; a second feedback switch for selectively connecting a second end of said second feedback capacitor to one of said reference voltage terminal and said ground voltage terminal; means for applying an input analog signal between second ends of said first and second sample capacitors in a balanced manner; first switch means for connecting one of said first and second common lines to said first input terminal of said integrator; second switch means for connecting the other of said first and second common lines to said second input terminal of said integrator; a comparator having first and second input terminals; said first and second input terminal of said comparator being connected to said first and second output terminals of said integrator; a counter circuit; first control means for controlling said counter circuit in response to the output of said comparator; second control means responsive to the output of said counter circuit for controlling said first to n-th switches of said first and second switch arrangements; third control means for controlling said first and second feedback capacitors in response to the output of said comparator; and fourth control means responsive to the outputs of said comparator and said counter circuit for controlling said first switch means and said second switch means.

Claim 5

An analog to digital converter, comprising; a balanced type integrator having a first input terminal, a second input terminal, a first output terminal and a second output terminal; first and second analog signal input terminals; a reference voltage terminal; a ground voltage terminal; first and second capacitor arrays, each of said capacitor arrays including first to n-th (n being a positive integer greater than 2) capacitors having weighted capacitances, the i-th capacitor having a capacitance 2 i-1 ×C (C being constant); first and second feedback capacitors; first and second sample capacitors, a first common line connected to first ends of said first to n-th capacitors of said first capacitor array said first feedback capacitor and said first sample capacitor; a second common line connected to first ends of said first to n-th capacitors of said second capacitor array, said second feedback capacitor and said second sample capacitor; a first switch arrangement including first to n-th switches provided for said first capacitor array, one of said first to n-th switches of said first switch arrangement selectively connecting a second end of one of said first to n-th capacitors of said first capacitor array to one of said reference voltage terminal and said ground voltage terminal; a second switch arrangement including first to n-th switches provided for said second capacitor array, one of said first to n-th switches of said second switch arrangement selectively connecting a second end of one of said first to n-th capacitors of said second capacitor array to one of said reference voltage terminal and said ground voltage terminal; a first feedback switch for selectively connecting a second end of said first feedback capacitor to one of said reference voltage terminal and said ground voltage terminal; a second feedback switch for selectively connecting a second end of said second feedback capacitor to one of said reference voltage terminal and said ground voltage terminal; means for applying an input analog signal between second ends of said first and second sample capacitors in a balanced manner; first switch means for connecting one of said first and second common lines to said first input terminal of said integrator; second switch means for connecting the other of said first and second common lines to said second input terminal of said integrator; a comparator having first and second input terminals; said first and second input terminal of said comparator being connected to said first and second output terminals of said integrator; a counter circuit; first control means for controlling said counter circuit in response to the output of said comparator; second control means responsive to the output of said counter circuit for controlling said first to n-th switches of said first and second switch arrangements; third control means for controlling said first and second feedback capacitors in response to the output of said comparator; and fourth control means responsive to the outputs of said comparator and said counter circuit for controlling said first switch means and said second switch means.

Claim 6

The analog to digital converter according to claim 3, in which said fourth control means includes a flip-flop whose state is reversed each time the content of said counter is zero and the polarity of the output of said comparator is changed.

Claim 7

The analog to digital converter according to claim 3, in which said first and second feedback capacitors have a capacitance in the range between half the capacitance of said first capacitor and twice the capacitance of said first capacitor.

Claim 8

The analog to digital converter according to claim 3, in which said first and second sample capacitors have a capacitance of 2 N ×C, C being a capacitance of said first capacitor.