Distributed digital signal process multiplexer

Claim 1

A digital signal processor multiplexer for ultra high frequencies, comprising: a plurality of GaAs field effect transistors each having a first and second gate input and a drain output, a biasing network coupled to the drain of each of said transistors and providing a termination network, a distributed transmission line having a delay line portion, delay taps connected to said delay line portion and to the second gate of each of said GaAs transistors, each said delay line tap being spaced apart from another delay tap by a desired time data rate period 1/τ, an ultra high frequency clock pulse source coupled to one end of said transmission line, a termination network coupled to the other end of said transmission line, data input channels each being coupled to one of said first gates of said GaAs transistors so that the presence of an input data pulse at an input channel simultaneously with a clock pulse on said data transmission line at the second gate of said transistors produces an output data pulse having the width of said clock pulses at the drain of said GaAs transistors, output transmission lines each coupled at one of its ends to the drain of one of said GaAs transistors, a combining network coupled to the other end of each of said output transmission lines providing a matched termination network, and a data output line coupled to said combining network for providing an output data rate which is a multiple of the rate of said input data pulses.