Memory assembly with cooling insert

Claim 2

A memory system assembly, said assembly comprising: an input interconnection network substrate having a system input electrical connector pair first member affixed at a first edge portion thereof which can be selectively mated with a system input electrical connector pair second member connected to external electrical apparatus to pass electrical signals therebetween, said input substrate first edge portion being located between input substrate second and third edge portions with said input substrate second edge portion having a first internal electrical connector pair first member affixed thereto and with said input substrate third edge portion having a second internal electrical connector pair first member affixed thereto, there being electrical interconnections provided between each of said first and second internal electrical connector pair first members and said system input electrical connector pair first member; an output interconnection network substrate having a system output electrical connector pair first member affixed at a first edge portion thereof which can be selectively mated with a system output electrical connector pair second member connected to external electrical apparatus to pass electrical signals therebetween, said output substrate first edge portion being located between output substrate second and third edge portions with said output substrate second edge portion having a third internal electrical connector pair first member affixed thereto and with said output substrate third edge portion having a fourth internal connector pair first member affixed thereto, there being electrical interconnections provided between each said third and fourth internal electrical connector pair first members and said system output electrical connector first member; a first transmission interconnection network substrate having selected internal electrical connector pair second members affixed thereto including first and third internal electrical connection pair second members capable of being mechanically and electrically connected with said first and third internal electrical pair first members, respectively, there being electrical interconnections selectively provided between said plurality of internal electrical connector pair second members, said first and third internal electrical connector pair first members being mechanically and electrically connected with said first and third internal electrical connector pair second members, respectively; a second transmission interconnection network substrate having selected internal electrical connector pair second members affixed thereto including second and fourth internal electrical connector pair second members capable of being mechanically and electrically connected with said second and fourth internal electrical pair first members, respectively, there being electrical interconnections selectively provided between said plurality of internal electrical connector pair second members, said second and fourth internal electrical connector pair first members being mechanically and electrically connected with said second and fourth internal electrical connector pair second members, respectively; and a plurality of memory module interconnection network substrates each having a pair of internal electrical connector pair first members affixed at selected edges thereof one of which is capable of being, and is, mechanically and electrically connected with at least one of said selected internal electrical connector pair second members affixed to said first transmission interconnection network substrate, as aforesaid, and that one remaining capable of being, and is, mechanically and electrically connected with at least one of said selected internal electrical connector pair second members affixed to said second transmission interconnection network substrate, as aforesaid, each of said plurality of memory module interconnection network substrates having at least one electronic memory circuit means affixed thereto with each said electronic memory circuit means having an electrical interconnection to each of said internal electrical connector pair first members affixed thereto, as aforesaid, said connections of said internal electrical connector pair first and second members being solely relied upon to mechanically connect, in that manner aforesaid, said input, output, first transmission, second transmission and plurality of memory module interconnection network substrates.

Claim 3

The apparatus of claim 1 wherein said electronic memory circuit means is a monolithic integrated circuit.

Claim 4

The apparatus of claim 1 wherein each of said input and output interconnection network substrates and each of said plurality of memory module interconnection network substrates has a monolithic integrated circuit affixed thereto.

Claim 5

The apparatus of claim 1 wherein each of said input and output interconnection network substrates, said plurality of memory module interconnection network substrates, and said first and second transmission interconnection network substrates are formed with a plurality of dielectric layers separating a plurality of interconnection network portions.

Claim 6

The apparatus of claim 1 wherein at least some of those spaces occuring between members of said plurality of memory module interconnection network substrates and between members of said plurality of memory module interconnection network substrates and said input and output interconnection network substrates have substantially enclosed gas chambers located therein with openings in said gas chambers opposite said electronic memory circuit means so that if a pressurized gas is supplied to said gas chambers that gas escaping from said openings therein will impinge on said electronic memory circuit means.

Claim 7

The apparatus of claim 1 wherein each of said plurality of memory module interconnection network substrates is positioned between said input and output interconnection network substrates.

Claim 8

The apparatus of claim 1 wherein at least one interconnection in said first transmission interconnection network substrate is made commonly to each of said selected internal electrical connector pair second members affixed thereto.

Claim 9

The appartus of claim 1 wherein at least one interconnection in said second transmission interconnection network substrate is made commonly to each of said selected internal electrical connector pair second members affixed thereto.

Claim 10

The apparatus of claim 1 wherein said internal electrical connector pair first members are substantially identical to one another, and said internal electrical connector pair second members are substantially identical to one another.

Claim 11

The apparatus of claim 3 wherein each of said monolithic integrated circuits is positioned in those spaces occuring between any pair of said memory module interconnection network substrates and said input and output interconnection substrates.

Claim 12

The apparatus of claim 5 wherein each of said gas enclosure chambers opens into a common supply chamber adapted for connection to a source of pressurized gas.

Claim 13

The appartus of claim 7 wherein at least one interconnection in said second transmission interconnection network substrate is made commonly to each of said selected internal electrical connector pair second members affixed thereto.

Claim 14

The apparatus of claim 10 wherein at least some of those spaces occuring between members of said plurality of memory module interconnection network substrates and between members of said plurality of memory module interconnection network substrates and said input and output interconnection network substrates have substantially enclosed gas chambers located therein with openings in said gas chambers opposite said electronic memory circuit means so that if a pressurized gas is supplied to said gas chambers that gas escaping from said openings therein will impinge on said electronic memory circuit means.

Claim 15

The apparatus of claim 11 wherein at least one of said plurality of memory module interconnection substrates has a plurality of electronic memory circuit means affixed thereto in a column so that a said gas chamber on a said space adjacent such a memory module interconnection substrate, having a pair of linear protrusions from its surface, has one of said linear protrusions on either side of said column.

Claim 16

The apparatus of claim 12 wherein said internal electrical connector pair first members are substantially identical to one another, and said internal electrical connector pair second members are substantially identical to one another.

Claim 17

The apparatus of claim 13 wherein each of said plurality of memory module interconnection network substrates is positioned between said input and output interconnection network substrates.

Claim 18

The apparatus of claim 15 wherein each of said plurality of memory module interconnection network substrates is positioned between said input and output interconnection network substrates.

Claim 19

A memory system assembly, said assembly comprising: an input interconnection network substrate having a system input electrical connector pair first member affixed at a first edge portion thereof which can be selectively mated with a system input electrical connector pair second member connected to external electrical apparatus to pass electrical signals therebetween, said input substrate first edge portion being located between input substrate second and third edge portions with said input substrate second edge portion having a first internal electrical connector pair first member affixed thereto and with said input substrate third edge portion having a second internal electrical connector pair first member affixed thereto, there being electrical interconnections provided between each of said first and second internal electrical connector pair first members and said system input electrical connector pair first member; an output interconnection network substrate having a system output electrical connector pair first member affixed at a first edge portion thereof which can be selectively mated with a system output electrical connector pair second member connected to external electrical apparatus to pass electrical signals therebetween, said output substrate first edge portion being located between output substrate second and third edge portions with said output substrate second edge portion having a third internal electrical connector pair first member affixed thereto and with said output substrate third edge portion having a fourth internal connector pair first member affixed thereto, there being electrical interconnections provided between each said third and fourth internal electrical connector pair first members and said system output electrical connector first member; a first transmission interconnection network substrate having selected internal electrical connector pair second members affixed thereto including first and third internal electrical connection pair second members capable of being mechanically and electrically connected with said first and third internal electrical pair first members, respectively, there being electrical interconnections selectively provided between said plurality of internal electrical connector pair second members, said first and third internal electrical connector pair first members being mechanically and electrically connected with said first and third internal electrical connector pair second members, respectively; a second transmission interconnection network substrate having selected internal electrical connector pair second members affixed thereto including second and fourth internal electrical connector pair second members capable of being mechanically and electrically connected with said second and fourth internal electrical pair first members, respectively, there being electrical interconnections selectively provided between said plurality of internal electrical connector pair second members, said second and fourth internal electrical connector pair first members being mechanically and electrically connected with said second and fourth internal electrical connector pair second members, respectively; and a plurality of memory module interconnection network substrates each having a pair of internal electrical connector pair first members affixed at selected edges thereof one of which is capable of being, and is, mechanically and electrically connected with at least one of said selected internal electrical connector pair second members affixed to said first transmission interconnection network substrate, as aforesaid, and that one remaining capable of being, and is, mechanically and electrically connected with at least one of said selected internal electrical connector pair second members affixed to said second transmission interconnection network substrate, as aforesaid, each of said plurality of memory module interconnection network substrates having at least one electronic memory circuit means affixed thereto with each said electronic memory circuit means having an electrical interconnection to each of said internal electrical connector pair first members affixed thereto, as aforesaid; and a cooling insert means positioned in at least some of those spaces occuring between members of said plurality of memory module interconnection network substrates and said input and output interconnection network substrates, and having substantially enclosed gas chambers located therein with openings in said gas chambers opposite said electronic memory circuit means so that if a pressurized gas is supplied to said gas chambers that gas escaping from said openings therein will impinge on said electronic memory circuit means.

Claim 20

A memory system assembly, said assembly comprising: an input interconnection network substrate having a system input electrical connector pair first member affixed at a first edge portion thereof which can be selectively mated with a system input electrical connector pair second member connected to external electrical apparatus to pass electrical signals therebetween, said input substrate first edge portion being located between input substrate second and third edge portions with said input substrate second edge portion having a first internal electrical connector pair first member affixed thereto and with said input substrate third edge portion having a second internal electrical connector pair first member affixed thereto, there being electrical interconnections provided between each of said first and second internal electrical connector pair first members and said system input electrical connector pair first member; an output interconnection network substrate having a system output electrical connector pair first member affixed at a first edge portion thereof which can be selectively mated with a system output electrical connector pair second member connected to external electrical apparatus to pass electrical signals therebetween, said output substrate first edge portion being located between output substrate second and third edge portions with said output substrate second edge portion having a third internal electrical connector pair first member affixed thereto and with said output substrate third edge portion having a fourth internal connector pair first member affixed thereto, there being electrical interconnections provided between each said third and fourth internal electrical connector pair first members and said system output electrical connector first member; a first transmission interconnection network substrate having selected internal electrical connector pair second members affixed thereto including first and third internal electrical connection pair second members capable of being mechanically and electrically connected with said first and third internal electrical pair first members, respectively, there being electrical interconnections selectively provided between said plurality of internal electrical connector pair second members, said first and third internal electrical connector pair first members being mechanically and electrically connected with said first and third internal electrical connector pair second members, respectively; a second transmission interconnection network substrate having selected internal electrical connector pair second members affixed thereto including second and fourth internal electrical connector pair second members capable of being mechanically and electrically connected with said second and fourth internal electrical pair first members, respectively, there being electrical interconnections selectively provided between said plurality of internal electrical connector pair second members, said second and fourth internal electrical connector pair first members being mechanically and electrically connected with said second and fourth internal electrical connector pair second members, respectively; and a plurality of memory module interconnection network substrates each having a pair of internal electrical connector pair first members affixed at selected edges thereof one of which is capable of being, and is, mechanically and electrically connected with at least one of said selected internal electrical connector pair second members affixed to said first transmission interconnection network substrate, as aforesaid, and that one remaining capable of being, and is, mechanically and electrically connected with at least one of said selected internal electrical connector pair second members affixed to said second transmission interconnection network substrate, as aforesaid, each of said plurality of memory module interconnection network substrates having at least one electronic memory circuit means affixed thereto with each said electronic memory circuit means having an electrical interconnection to each of said internal electrical connector pair first members affixed thereto, as aforesaid; and a cooling insert means positioned in at least some of those spaces occuring between members of said plurality of memory module interconnection network substrates and said input and output interconnection network substrates, and having substantially enclosed gas chambers located therein with openings in said gas chambers opposite said electronic memory circuit means so that if a pressurized gas is supplied to said gas chambers that gas escaping from said openings therein will impinge on said electronic memory circuit means.

Claim 21

The apparatus of claim 18 wherein said electronic memory circuit means is a monolithic integrated circuit.

Claim 22

The apparatus of claim 18 wherein each of said input and output interconnection network substrates and each of said plurality of memory module interconnection network substrates has a monolithic integrated circuit affixed thereto.

Claim 23

The apparatus of claim 18 wherein each of said input and output interconnection network substrates, said plurality of memory module interconnection network substrates, and said first and second transmission interconnection network substrates are formed with a plurality of dielectric layers separating a plurality of interconnection network portions.

Claim 24

The apparatus of claim 18 wherein each of said plurality of memory module interconnection network substrates is positioned between said input and output interconnection network substrates.

Claim 25

The apparatus of claim 18 wherein at least one interconnection in said first transmission interconnection network substrate is made commonly to each of said selected internal electrical connector pair second members affixed thereto.

Claim 26

The appartus of claim 18 wherein at least one interconnection in said second transmission interconnection network substrate is made commonly to each of said selected internal electrical connector pair second members affixed thereto.

Claim 27

The apparatus of claim 18 wherein said internal electrical connector pair first members are substantially identical to one another, and said internal electrical connector pair second members are substantially identical to one another.

Claim 28

The apparatus of claim 18 wherein each of said gas enclosure chambers opens into a common supply chamber adapted for connection to a source of pressurized gas.

Claim 29

The apparatus of claim 20 wherein each of said monolithic integrated circuits is positioned in those spaces occuring between any pair of said memory module interconnection network substrates and said input and output interconnection substrates with said gas chambers located therein as aforesaid.

Claim 30

The apparatus of claim 23 wherein at least one interconnection in said second transmission interconnection network substrate is made commonly to each of said selected internal electrical connector pair second members affixed thereto.

Claim 31

The apparatus of claim 26 wherein at least one of said plurality of memory module interconnection substrates has a plurality of electronic memory circuit means affixed thereto in a column so that a said gas chamber on a said space adjacent such a memory module interconnection substrate, having a pair of linear protrusions from its surface, has one of said linear protrusions on either side of said column.

Claim 32

The apparatus of claim 28 wherein said internal electrical connector pair first members are substantially identical to one another, and said internal electrical connector pair second members are substantially identical to one another.

Claim 33

The apparatus of claim 30 wherein each of said plurality of memory module interconnection network substrates is positioned between said input and output interconnection network substrates.