Low phase noise RF synthesizer

Abstract

Abstract A low phase noise RF synthesizer comprises three phase-locked loops. In the preferred embodiment, the base RF signal, 980 to 1520 MHz in 20 MHz steps is generated by one loop, while the high resolution IF signal is generated by a fractional-N loop. The RF and IF signals are combined in a third phase-locked loop, the output sum loop, to produce the output signal. A programmable variable divider divides the IF output frequency, achieving coverage over the necessary frequency range by changing the divide number, so the fractional-N circuit only has to fill in the fine steps between the divide numbers. A reference input frequency in the fractional-N loop has each of the factors 2, 3, and 5 in its divisor, so that the output signal of the synthesizer can be multiplied by any of these factors without producing a fractional frequency. It will be appreciated that the advantages achieved by the aspects of the invention incorporated in certain portions of the synthesizer described have independent utility and could be used in a variety of synthesizer designs. This is particularly true for the variable divider, e.g., divider 191, in the IF reference loop output and for the multi-factor divider, e.g., divider 187, in the IF reference loop input.

Inventors

• 👤 Allen P. Edwards

Bibliographic Details