US4761816A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital level detecting circuit
Assignee: Sony Corp
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Filing: 1986-12-12
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Granted: 1988-08-02
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Expires: 2006-12-12
Abstract
Abstract A digital level detecting circuit for controlling amplitudes of digital audio signals is disclosed, which includes a circuit for generating an attack response of output control signals based on positive going waveforms of an incoming signal and attack response coefficients stored in a memory, and wherein the attack response coefficients stored in the memory are limited to a lower value than the theoretical value at the beginning of the attack response.
Inventors
- 👤 Hideki Fukasawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:01
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
97 words
A digital level detecting circuit for controlling the amplitude of digital audio signals, comprising: means for generating an attack response of output control signals based on positive going waveforms of an incoming signal and based on attack response coefficients stored in a memory, wherein the attack response coefficients stored in said memory have a relatively low value during the beginning of the attack response, and wherein said attack response generating means includes an address generator which generates address data to be supplied to said memory based on ratios of the incoming signal and the output control signals.
Claim 2
Dependent Claim
97 words
A digital level detecting circuit for controlling the amplitude of digital audio signals, comprising: means for generating an attack response of output control signals based on positive going waveforms of an incoming signal and based on attack response coefficients stored in a memory, wherein the attack response coefficients stored in said memory have a relatively low value during the beginning of the attack response, and wherein said attack response generating means includes an address generator which generates address data to be supplied to said memory based on ratios of the incoming signal and the output control signals.
Claim 3
Dependent Claim
59 words
A digital level detecting circuit according to claim 1, wherein said attack response generating means further includes a multiplier circuit which multiplies said incoming signal and said attack response coefficients from said memory, and the outputs of said multiplier circuit are supplied to an output terminal for said output control signal through an adder circuit and a timing circuit.
Claim 4
Dependent Claim
33 words
A digital level detecting circuit according to claim 2, wherein said adder circuit of the attack response generating means is supplied with said outputs from said multiplier circuit and an output control signal.
Claim 5
Dependent Claim
50 words
A digital level detecting circuit according to claim 1, wherein said attack response generating means includes a subtracter circuit for obtaining the difference between said incoming signal and said output control signal, and said difference is multiplied by said attack response coefficients obtained from said memory in a multiplier circuit.
Claim 6
Dependent Claim
35 words
A digital level detecting circuit according to claim 4, wherein the outputs from said multiplier circuit are supplied to an output terminal for said output control signal through an adder circuit and a timing circuit.
Claim 7
Dependent Claim
33 words
A digital level detecting circuit according to claim 5, wherein said adder circuit of said attack response generating means is supplied with said outputs from said multiplier circuit and an output control signal.
Claim 8
Dependent Claim
101 words
A digital level detecting circuit for controlling the amplitude of digital audio signals, comprising: means for generating an attack response of output control signals based on positive going waveforms of an incoming signal and based on attack response coefficients stored in a memory, wherein the attack response coefficients stored in said memory have a relatively low value during the beginning of the attack response, and further comprising means for generating hold and recovery response of said output control signals based on negative going waveforms of the incoming signal and hold and recovery coefficients, and wherein said hold coefficients are not zero.
Claim 9
Dependent Claim
101 words
A digital level detecting circuit for controlling the amplitude of digital audio signals, comprising: means for generating an attack response of output control signals based on positive going waveforms of an incoming signal and based on attack response coefficients stored in a memory, wherein the attack response coefficients stored in said memory have a relatively low value during the beginning of the attack response, and further comprising means for generating hold and recovery response of said output control signals based on negative going waveforms of the incoming signal and hold and recovery coefficients, and wherein said hold coefficients are not zero.
Claim 10
Dependent Claim
27 words
A digital level detecting circuit according to claim 7, wherein said hold and recovery response generating means includes a memory for storing said hold and recovery coefficients.
References Cited (Backward Citations)
US4520708A
Cited
US4611344A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-02 | 1992-02-01 | 1992-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-02 | 1996-02-01 | 1996-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-02 | 2000-02-01 | 2000-08-02 | $7700.00 | Window Closed / Lapsed |