Cipher system

Claim 2

A cipher system comprising an encipherment section and a decipherment section, the encipherment section comprising: a first shift register storing latest k bits of ciphertext information, a first register storing k bits of cipher key, a first modulo-2 adder means for adding, bit by bit, the k-bit contents of the first shift register and the k-bit contents of the first register, a first expander means for expanding the k-bit output of the first modulo-2 adder means into m×n bits, a second register for storing the m×n-bit output of the first expander means, a first controller means for performing control to extract the contents of the second register in sequence, a set of n bits at a time, a first code converter means receiving the output of the second register as extracted in turn by the first controller means, and converting each set of n bits into a single bit, a third register, a second modulo-2 adder means for adding the 1 bit output of the first code converter means to the contents of the third register, the third register storing the output of the second adder means, a fourth register for storing the output of the second adder means, a fifth register for storing plaintext information input through the input terminal, a third modulo-2 adder means for adding the contents of the fourth register to the contents of the fifth register to produce ciphertext information, a sixth register for storing the output of the third adder, a first feedback means for feeding back the contents of the sixth register to the first shift register, a first output means for outputting the contents of the sixth register as ciphertext information, and a first control signal generator means for generating control signals to control operation of various elements of the encipherment section, the decipherment section comprising: a second shift register storing latest k bits of ciphertext information, a seventh register storing k bits of cipher key, a fourth modulo-2 adder means for adding, bit by bit, the k-bit contents of the second shift register and the k-bit contents of the seventh register, a second expander means for expanding the k-bit output of the fourth modulo-2 adder means into m×n bits, an eighth register for storing the m×n-bit output of the second expander means, a second controller means for performing control to extract the contents of the eighth register in sequence, a set of n bits at a time, a second code converter means receiving the output of the eighth register as extracted in turn by the second controller means, and converting each set of n bits into a single bit, a ninth register, a fifth modulo-2 adder means for adding the 1 bit output of the second code converter means to the contents of the ninth register, the ninth register storing the output of the fifth adder means, a tenth register for storing the output of the fifth adder means, an eleventh register for storing ciphertext information input through the input terminal, a sixth modulo-2 adder means for adding the contents of the tenth register to the contents of the eleventh register to produce ciphertext information, a twelfth register for storing the output of the sixth adder, a second feedback means for feeding back the contents of the eleventh register to the second shift register, a second output means for outputting the contents of the twelfth register as deciphered text information, and a second control signal generator means for generating control signals to control operation of various elements of the encipherment section, where k, m and n are integers satisfying m×n>k.

Claim 3

A terminal for use in a cipher system, said terminal comprising an encipherment section and a decipherment section, said encipherment section comprising: a first shift register storing latest k bits of ciphertext information, a first register storing k bits of cipher key, a first modulo-2 adder means for adding, bit by bit, the k-bit contents of the first shift register and the k-bit contents of the first register, a first expander means for expanding the k-bit output of the first modulo-2 adder means into m×n bits, a second register for storing the m×n-bit output of the first expander means, a first controller means for performing control to extract the contents of the second register in sequence, a set of n bits at a time, a first code converter means receiving the output of the second register as extracted in turn by the first controller means, and converting each set of n bits into a single bit, a third register, a second modulo-2 adder means for adding the 1 bit output of the first code converter means to the contents of the third register, the third register storing the output of the second adder means, a fourth register for storing the output of the second adder means, a fifth register for storing plaintext information input through the input terminal, a third modulo-2 adder means for adding the contents of the fourth register to the contents of the fifth register to produce ciphertext information, a sixth register for storing the output of the third adder, a first feedback means for feeding back the contents of the sixth register to the first shift register, a first output means for outputting the contents of the sixth register as ciphertext information, and a first control signal generator means for generating control signals to control operation of various elements of the encipherment section, said decipherment section comprising: a second shift register storing latest k bits of ciphertext information, a seventh register storing k bits of cipher key, a fourth modulo-2 adder means for adding, bit by bit, the k-bit contents of the second shift register and the k-bit contents of the seventh register, a second expander means for expanding the k-bit output of the fourth modulo-2 adder means into m×n bits, an eighth register for storing the m×n-bit output of the second expander means, a second controller means for performing control to extract the contents of the eighth register in sequence, a set of n bits at a time, a second code converter means receiving the output of the eighth register as extracted in turn by the second controller means, and converting each set of n bits into a single bit, a ninth register, a fifth modulo-2 adder means for adding the 1 bit output of the second code converter means to the contents of the ninth register, the ninth register storing the output of the fifth adder means, a tenth register for storing the output of the fifth adder means, an eleventh register for storing ciphertext information input through the input terminal, a sixth modulo-2 adder means for adding the contents of the tenth register to the contents of the eleventh register to produce ciphertext information, a twelfth register for storing the output of the sixth adder, a second feedback means for feeding back the contents of the eleventh register to the second shift register; a second output means for outputting the contents of the twelfth register as deciphered text information, and a second control signal generator means for generating control signals to control operation of various elements of the encipherment section, where k, m and n are integers satisfying m×n>k.

Claim 4

A terminal for use in a cipher system, said terminal comprising an encipherment section and a decipherment section, said encipherment section comprising: a first shift register storing latest k bits of ciphertext information, a first register storing k bits of cipher key, a first modulo-2 adder means for adding, bit by bit, the k-bit contents of the first shift register and the k-bit contents of the first register, a first expander means for expanding the k-bit output of the first modulo-2 adder means into m×n bits, a second register for storing the m×n-bit output of the first expander means, a first controller means for performing control to extract the contents of the second register in sequence, a set of n bits at a time, a first code converter means receiving the output of the second register as extracted in turn by the first controller means, and converting each set of n bits into a single bit, a third register, a second modulo-2 adder means for adding the 1 bit output of the first code converter means to the contents of the third register, the third register storing the output of the second adder means, a fourth register for storing the output of the second adder means, a fifth register for storing plaintext information input through the input terminal, a third modulo-2 adder means for adding the contents of the fourth register to the contents of the fifth register to produce ciphertext information, a sixth register for storing the output of the third adder, a first feedback means for feeding back the contents of the sixth register to the first shift register, a first output means for outputting the contents of the sixth register as ciphertext information, and a first control signal generator means for generating control signals to control operation of various elements of the encipherment section, said decipherment section comprising: a second shift register storing latest k bits of ciphertext information, a seventh register storing k bits of cipher key, a fourth modulo-2 adder means for adding, bit by bit, the k-bit contents of the second shift register and the k-bit contents of the seventh register, a second expander means for expanding the k-bit output of the fourth modulo-2 adder means into m×n bits, an eighth register for storing the m×n-bit output of the second expander means, a second controller means for performing control to extract the contents of the eighth register in sequence, a set of n bits at a time, a second code converter means receiving the output of the eighth register as extracted in turn by the second controller means, and converting each set of n bits into a single bit, a ninth register, a fifth modulo-2 adder means for adding the 1 bit output of the second code converter means to the contents of the ninth register, the ninth register storing the output of the fifth adder means, a tenth register for storing the output of the fifth adder means, an eleventh register for storing ciphertext information input through the input terminal, a sixth modulo-2 adder means for adding the contents of the tenth register to the contents of the eleventh register to produce ciphertext information, a twelfth register for storing the output of the sixth adder, a second feedback means for feeding back the contents of the eleventh register to the second shift register; a second output means for outputting the contents of the twelfth register as deciphered text information, and a second control signal generator means for generating control signals to control operation of various elements of the encipherment section, where k, m and n are integers satisfying m×n>k.

Claim 5

A terminal acording to claim 2, wherein said first register is also used as said seventh register, said first adder means is also used as said fourth adder means, said first expander means is also used as said second expander means, said second register is also used as said eighth register, said first controller means is also used as said second controller means, said first code converter means is also used as said second code converter means, said second adder means is also used as said fifth adder means, said third register is also used as said ninth register the encipherment section and the decipherment section using the above elements in a time-sharing manner.

Claim 6

A terminal according to claim 3 further comprising switching means for selective connection of the elements shared by the encipherment section and the decipherment section, either for operation for encipherment or for decipherment.