US4760249A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic array having multiple optical logic inputs
Assignee: NXP USA Inc
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Filing: 1986-12-22
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Granted: 1988-07-26
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Expires: 2006-12-22
Abstract
Abstract A monolithically integrated logic circuit is provided that is programmed by an optical input. A plurality of input/output pads are provided on a semiconductor substrate having a planar surface. A plurality of semiconductor devices and a plurality of light sensitive devices are formed with selected patterns in the surface. At least one metallic layer is formed on the substrate for coupling selected ones of the semiconductor devices, light sensitive devices, and input/output pads for forming a logic circuit, wherein an output of the logic circuit is determined by programming selected ones of the plurality of light sensitive devices by applying light thereto.
Inventors
- 👤 Ira E. Baskett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736; H03K19/14
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
114 words
A monolithically integrated logic array comprising: a semiconductor substrate having a planar surface; a plurality of input/output pads provided on said surface; a plurality of semiconductor devices formed with selected patterns in said surface; a plurality of electromagnetic sensitive devices formed with selected patterns in said surface; and at least one metallic layer formed on said substrate, said at least one metallic layer coupling selected ones of said semiconductor devices, electromagnetic sensitive devices, and input/output pads for forming said logic array, wherein at least one output signal at one of said input/output pads is at least partially determined by programming selected ones of said plurality of electromagnetic sensitive devices by applying electromagnetic waves thereto.
Claim 2
Dependent Claim
114 words
A monolithically integrated logic array comprising: a semiconductor substrate having a planar surface; a plurality of input/output pads provided on said surface; a plurality of semiconductor devices formed with selected patterns in said surface; a plurality of electromagnetic sensitive devices formed with selected patterns in said surface; and at least one metallic layer formed on said substrate, said at least one metallic layer coupling selected ones of said semiconductor devices, electromagnetic sensitive devices, and input/output pads for forming said logic array, wherein at least one output signal at one of said input/output pads is at least partially determined by programming selected ones of said plurality of electromagnetic sensitive devices by applying electromagnetic waves thereto.
Claim 3
Dependent Claim
42 words
The circuit according to claim 1 wherein said plurality of semiconductor devices comprise a plurality of flip-flops, each of said flip-flops coupled to one of said electromagnetic sensitive devices, wherein said circuit will remain programmed after said electromagnetic waves have been removed.
Claim 4
Dependent Claim
30 words
The circuit according to claim 1 further comprising at least one electromagnetic voltage device coupled to at least one of said electromagnetic sensitive devices for providing a supply voltage thereto.
Claim 5
Dependent Claim
30 words
The circuit according to claim 1 further comprising at least one electromagnetic voltage device coupled to at least one of said electromagnetic sensitive devices for providing a reference voltage thereto.
Claim 6
Dependent Claim
56 words
The circuit according to claim 1 wherein said plurality of semiconductor devices comprise a logic gate and at least one of said electromagnetic sensitive devices is a diode having an anode coupled to a first voltage and a cathode coupled to a second voltage, said logic gate coupled to one of said anode and said cathode.
Claim 7
Dependent Claim
64 words
The circuit according to claim 1 wherein said plurality of semiconductor devices comprise a logic gate and at least one of said electromagnetic sensitive devices is a transistor having a first current carrying electrode coupled to said logic gate and a second current carrying electrode coupled to a first voltage, and further comprising a resistor coupled between said logic gate and a second voltage.
Claim 8
Dependent Claim
88 words
A monolithically integrated logic array comprising: a plurality of logic gates, each of said logic gates having an input for receiving a digital input and an output for providing a digital output; first means for providing a first voltage; second means for providing a second voltage; a plurality of third means, each of said third means coupled between said first and second means and coupled to one of said plurality of logic gates for providing said digital input to said logic gate in response to an electromagnetic input.
Claim 9
Dependent Claim
88 words
A monolithically integrated logic array comprising: a plurality of logic gates, each of said logic gates having an input for receiving a digital input and an output for providing a digital output; first means for providing a first voltage; second means for providing a second voltage; a plurality of third means, each of said third means coupled between said first and second means and coupled to one of said plurality of logic gates for providing said digital input to said logic gate in response to an electromagnetic input.
Claim 10
Dependent Claim
41 words
The monolithically integrated logic array according to claim 7 wherein each one of said third means comprises an electromagnetic sensitive diode having an anode coupled to said first means and a cathode coupled to said second means and said logic gate.
Claim 11
Dependent Claim
42 words
The monolithically integrated logic circuit according to claim 7 wherein each one of said third means comprises: a resistor coupled between said first means and said logic gate; and an electromagnetic sensitive transistor coupled between said logic gate and said second means.
Claim 12
Dependent Claim
37 words
The monolithically integrated logic circuit according to claim 7 further comprising a plurality of fourth means, each of said fourth means coupled between one of said third means and said logic gate for latching said input signal.
Claim 13
Dependent Claim
18 words
The monolithically integrated logic circuit according to claim 7 wherein said first means comprises an electromagnetic sensitive device.
Claim 14
Dependent Claim
93 words
A gate array including a plurality of logic gates on an integrated circuit, a plurality of input/output pins, at least one metallization layer formed on said integrated circuit and coupling selected ones of said logic gates and input/output pads for forming a logic circuit, said gate array comprising: a plurality of electromagnetic sensitive devices formed on said integrated circuit, coupled to said logic gates by said metallization layer, wherein an output of said logic circuit is determined by programming selected ones of said plurality of electromagnetic sensitive devices by applying electromagnetic waves thereto.
Claim 15
Dependent Claim
93 words
A gate array including a plurality of logic gates on an integrated circuit, a plurality of input/output pins, at least one metallization layer formed on said integrated circuit and coupling selected ones of said logic gates and input/output pads for forming a logic circuit, said gate array comprising: a plurality of electromagnetic sensitive devices formed on said integrated circuit, coupled to said logic gates by said metallization layer, wherein an output of said logic circuit is determined by programming selected ones of said plurality of electromagnetic sensitive devices by applying electromagnetic waves thereto.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-26 | 1992-01-25 | 1992-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-26 | 1996-01-25 | 1996-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-26 | 2000-01-25 | 2000-07-26 | $7700.00 | Window Closed / Lapsed |