US4758737A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock generator circuit
Assignee: Sharp Corp
•
Filing: 1987-07-20
•
Granted: 1988-07-19
•
Expires: 2007-07-20
Abstract
Abstract A clock generator circuit of this invention is for an integrated circuit which is controlled by clock signals obtained by frequency-dividing a standard clock. Three flip-flops, two of which are connected in series, and two logical gates together form a synchronization circuit such that when a command signal is inputted to start testing the integrated circuit, frequency-divided clock signals in synchronism with a standard clock are outputted.
Inventors
- 👤 Takaaki Hirano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:11
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
178 words
A clock generator circuit for an integrated circuit controlled by a frequency-divided clock obtained by frequency-dividing a standard clock, comprising a first flip-flop with a true output and a false output, a second flip-flop connected to said true output and said false output of said first flip-flop and having a second output, a first logical gate with first gate inputs and a first gate output, said first gate inputs being connected each to said false output of said first flip-flop and to said second output of said second flip-flop, a third flip-flop having a clock signal output terminal from which clock signal for operating an integrated circuit is outputted, and a second logical gate with second gate inputs and a second gate output, said second gate inputs being connected each to said clock signal output terminal of said third flip-flop and said first gate output and said second gate output being connected to said third flip-flop, said first flip-flop, said second flip-flop and said third flip-flop each having a clock input terminal connected to receive said standard clock.
Claim 2
Dependent Claim
178 words
A clock generator circuit for an integrated circuit controlled by a frequency-divided clock obtained by frequency-dividing a standard clock, comprising a first flip-flop with a true output and a false output, a second flip-flop connected to said true output and said false output of said first flip-flop and having a second output, a first logical gate with first gate inputs and a first gate output, said first gate inputs being connected each to said false output of said first flip-flop and to said second output of said second flip-flop, a third flip-flop having a clock signal output terminal from which clock signal for operating an integrated circuit is outputted, and a second logical gate with second gate inputs and a second gate output, said second gate inputs being connected each to said clock signal output terminal of said third flip-flop and said first gate output and said second gate output being connected to said third flip-flop, said first flip-flop, said second flip-flop and said third flip-flop each having a clock input terminal connected to receive said standard clock.
Claim 3
Dependent Claim
25 words
The clock generator circuit of claim 1 wherein said first logical gate is a NOR gate and said second logical gate is another NOR gate.
Claim 4
Dependent Claim
25 words
The clock generator circuit of claim 1 wherein said first logical gate is an OR gate and said second logical gate is a NAND gate.
Claim 5
Dependent Claim
19 words
The clock generator circuit of claim 1 wherein said first, second and third flip-flops each include a D flip-flop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-19 | 1992-01-18 | 1992-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-19 | 1996-01-18 | 1996-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-19 | 2000-01-18 | 2000-07-19 | $7700.00 | Window Closed / Lapsed |