Automatic gain control method and circuit for a time division multiple access receiver

Claim 3

A method according to claim 1, using automatic gain control having a reaction time of a few hundred nanoseconds on data packets having a preamble which lasts for several microseconds.

Claim 4

An automatic gain control circuit for a time division multiple access (TDMA) receiver, said receiver receiving data packets in successions from one or more transmitter stations, each packet comprising, in succession, a preamble and then a data sequence, said preamble beginning at least with a first portion for enabling the receiver to recover the frequency of a signal carrier wave, and implementing a method of providing automatic gain control by performing automatic gain control on at least a part of said first portion of said preamble, storing the amplitude of the AGC voltage during the period that said automatic gain control is being performed, and interrupting said automatic gain control while allowing said stored AGC voltage to act on the received signal, at least for the remainder of said packet, and wherein said automatic gain control has a reaction time which is very much less than the time available for the automatic gain control to act on said part of said first portion of said preamble, said circuit comprising: a direct transmission path for the useful signal, said path being equipped with a controlled attenuator having a very short response time relative to the duration of said preamble; a first feedback loop for controlling the attenuator and comprising in succession a highspeed detector, a comparator receiving a reference AGC voltage, a highspeed controlled sampler, and storage means for storing the output signal from said control sampler; and a second feedback loop for controlling said controlled samples and comprising, in parallel, a first path including a at least one narrow band filter centered on a pure frequency conveyed by said first portion of said preamble, and a second path comprising in succession a highspeed detector and a comparator which additionally receives a reference voltage, both of said paths being connected to respective input terminals to an OR gate whose output is connected to the control input of said highspeed sampler.

Claim 5

An automatic gain control circuit for a time division multiple access (TDMA) receiver, said receiver receiving data packets in successions from one or more transmitter stations, each packet comprising, in succession, a preamble and then a data sequence, said preamble beginning at least with a first portion for enabling the receiver to recover the frequency of a signal carrier wave, and implementing a method of providing automatic gain control by performing automatic gain control on at least a part of said first portion of said preamble, storing the amplitude of the AGC voltage during the period that said automatic gain control is being performed, and interrupting said automatic gain control while allowing said stored AGC voltage to act on the received signal, at least for the remainder of said packet, and wherein said automatic gain control has a reaction time which is very much less than the time available for the automatic gain control to act on said part of said first portion of said preamble, said circuit comprising: a direct transmission path for the useful signal, said path being equipped with a controlled attenuator having a very short response time relative to the duration of said preamble; a first feedback loop for controlling the attenuator and comprising in succession a highspeed detector, a comparator receiving a reference AGC voltage, a highspeed controlled sampler, and storage means for storing the output signal from said control sampler; and a second feedback loop for controlling said controlled samples and comprising, in parallel, a first path including a at least one narrow band filter centered on a pure frequency conveyed by said first portion of said preamble, and a second path comprising in succession a highspeed detector and a comparator which additionally receives a reference voltage, both of said paths being connected to respective input terminals to an OR gate whose output is connected to the control input of said highspeed sampler.

Claim 6

An AGC circuit according to claim 3, in which said highspeed attenuator and said highspeed detectors have a response time of about 1 nanosecond.

Claim 7

An AGC circuit according to claim 3, wherein said highspeed attenuator comprises a ring mixer.

Claim 8

An AGC circuit according to claim 3, wherein said highspeed attenuator is constituted by a plurality of ring mixers connected in series and controlled in parallel.