US4757470A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pattern generation for a graphics display
Assignee: Bull HN Information Systems Inc
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Filing: 1987-07-01
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Granted: 1988-07-12
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Expires: 2007-07-01
Abstract
Abstract A display subsystem having a graphics capability includes a bit map memory for storing bits, each bit representing a displayed pixel. A read only memory stores words, each word representative of a pixel of a selected pattern which is used to fill out an area of the display thereby clearly identifying adjacent areas of the display to the operator. The selected patterns are displayed in a REPLACE, an OR or an EXCLUSIVE OR mode of operation.
Inventors
- 👤 Kenneth E. Bruce
- 👤 Thomas O. Holtey
- 👤 Gary J. Goss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:21
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/393
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
293 words
A display subsystem includes apparatus for displaying predetermined patterns in an area of a display, said apparatus comprising: read only memory means for storing words specifying predetermined patterns, a predetermined number of words specifying each of said predetermined patterns; bit map memory means for storing a plurality of bits; microprocessor means coupled to said read only memory means and said bit map memory means for generating a first plurality of address signals for addressing a first memory location and subsequent memory locations of said read only memory means for reading out said predetermined number of words specifying said each of said predetermined patterns, and generating a second plurality of address signals for addressing a second memory location and subsequent memory locations for reading out a predetermined number of said plurality of bits, each corresponding to one of said predetermined number of words, said microprocessor means further including register means for storing a plurality of mode signals for selecting a REPLACE, OR or EXCLUSIVE OR mode of operation; and logic means coupled to said read only memory means, said bit map memory means and said microprocessor means, and responsive to a first mode signal to logically combine each of said predetermined words with each of said predetermined number of corresponding bits to generate a new bit signal, said bit map memory means having means responsive to said new bit signal for writing a new bit in each location of said bit map memory means specified by said second plurality of address signals; display means coupled to said bit map memory means for displaying a plurality of pixels each corresponding to said new bit in said each location of said bit map memory means, said plurality of pixels displaying said each of said predetermined patterns.
Claim 2
Dependent Claim
293 words
A display subsystem includes apparatus for displaying predetermined patterns in an area of a display, said apparatus comprising: read only memory means for storing words specifying predetermined patterns, a predetermined number of words specifying each of said predetermined patterns; bit map memory means for storing a plurality of bits; microprocessor means coupled to said read only memory means and said bit map memory means for generating a first plurality of address signals for addressing a first memory location and subsequent memory locations of said read only memory means for reading out said predetermined number of words specifying said each of said predetermined patterns, and generating a second plurality of address signals for addressing a second memory location and subsequent memory locations for reading out a predetermined number of said plurality of bits, each corresponding to one of said predetermined number of words, said microprocessor means further including register means for storing a plurality of mode signals for selecting a REPLACE, OR or EXCLUSIVE OR mode of operation; and logic means coupled to said read only memory means, said bit map memory means and said microprocessor means, and responsive to a first mode signal to logically combine each of said predetermined words with each of said predetermined number of corresponding bits to generate a new bit signal, said bit map memory means having means responsive to said new bit signal for writing a new bit in each location of said bit map memory means specified by said second plurality of address signals; display means coupled to said bit map memory means for displaying a plurality of pixels each corresponding to said new bit in said each location of said bit map memory means, said plurality of pixels displaying said each of said predetermined patterns.
Claim 3
Dependent Claim
65 words
The apparatus of claim 1 wherein said microprocessor means comprises: a microprocessor for generating said first plurality of address signals for addressing said first location of said read only memory means, said microprocessor generating said second plurality of address signals for addressing said second location of said bit map memory means, said microprocessor further generating a plurality of data signals defining said mode of operation.
Claim 4
Dependent Claim
118 words
The apparatus of claim 2 wherein said register means for selecting said mode of operation comprises: a register coupled to said microprocessor for storing said plurality of data signals and generating said first mode signal and a second mode signal of said plurality of mode signals wherein said first mode signal in a second state and said second mode signal in a second state define said REPLACE mode of operation, said first mode signal in said second state and said second mode signal in a first state define said OR mode of operation, and said first mode signal in a first state and said second mode signal in said second state define said EXCLUSIVE OR mode of operation.
Claim 5
Dependent Claim
37 words
The apparatus of claim 1 wherein said first plurality of addressing signals includes signals specifying said one of said predetermined patterns, signals specifying said word within said one of said predetermined patterns and said second mode signal.
Claim 6
Dependent Claim
44 words
The apparatus of claim 4 wherein the logic means comprises multiplexer means responsive to said first mode signal wherein bits of a word from the read only memory means are selected to be logically combined with a bit from the bit map memory means.
Claim 7
Dependent Claim
64 words
The apparatus of claim 5 wherein the logic means further comprises an AND gate for receiving one of the bits of the word from the read only memory and the bit from the bit map memory means and an EXCLUSIve OR gate for receiving another of the bits of the word from the read only memory means and the output of the AND gate.
Claim 8
Dependent Claim
88 words
The apparatus of claim 6 wherein the bit selected by said multiplexer means to be applied to the EXCLUSIVE OR gate from the read only memory means is the value of the pixel of the predetermined pattern to be displayed and the bit selected by said multiplexer means to be applied to the AND gate is a zero for a REPLACE mode, a one for an EXCLUSIVE OR mode, and the value opposite to that of the pixel of the predetermined pattern in an OR mode of operation.
Claim 9
Dependent Claim
44 words
The apparatus of claim 1 wherein the logic means comprises multiplexer means responsive to said first mode signal wherein bits of a word from the read only memory means are selected to be logically combined with a bit from the bit map memory means.
Claim 10
Dependent Claim
64 words
The apparatus of claim 8 wherein the logic means further comprises an AND gate for receiving one of the bits of the word from the read only memory and the bit from the bit map memory means and an EXCLUSIVE OR gate for receiving another of the bits of the word from the read only memory means and the output of the AND gate.
Claim 11
Dependent Claim
88 words
The apparatus of claim 9 wherein the bit selected by said multiplexer means to be applied to the EXCLUSIVE OR gate from the read only memory means is the value of the pixel of the predetermined pattern to be displayed and the bit selected by said multiplexer means to be applied to the AND gate is a zero for a REPLACE mode, a one for an EXCLUSIVE OR mode, and the value opposite to that of the pixel of the predetermined pattern in an OR mode of operation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-12 | 1992-01-11 | 1992-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-12 | 1996-01-11 | 1996-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-12 | 2000-01-11 | 2000-07-12 | $7700.00 | Window Closed / Lapsed |