Method and apparatus for functional testing of a memory which is reprogrammable electrically word by word

Claim 2

Method for the functional testing of a memory being electrically programmable word by word and including storage cells having storage transistors of such given widths of the reading windows during normal operation, that the programming times remain short during the specified life of the cells, which comprises reducing first the width of the reading windows of the storage transistors during a functional test, as compared to the given width during normal operation, and determining next if the memory contents can be read correctly, and rejecting the memory if the memory contents cannot be read correctly.

Claim 3

Method according to claim 1, which comprises reducing the width of the reading windows by at least 50% as compared to the given width.

Claim 4

Method according to claim 1, which comprises reducing the width of the reading windows by at least 80% as compared to the given width.

Claim 5

Method according to claim 1, which comprises reducing the width of the reading windows through a time control of an erasing and writing cycle.

Claim 6

Method according to claim 1, wherein the memeory has an addressing circuit for addressing the storage cells and control means for determinng the limit of successfful function in at least one of a predetermined erase and write state of at least one storage cell, which comprises operating the addressing circuit with different erase and writing times, and terminating the erase and writing times when the limit of successful function in at least one of the predetermined erase and write state of said at least one storage cell of the memory is determined by said control means.

Claim 7

Method according to claim 5, which comprises determining the successful function of the predetermined erase state by comparing a threshold voltage of a storage transistor with a predetermined erase test voltage.

Claim 8

Method according to claim 5, which comprises determining the successful function of the predetermined write state by comparing a threshold voltage of a storage transistor with a predetermined write test voltage.

Claim 9

Method according to claim 1, which comprises adjusting the reduction of the read window during the functional test by changing control voltages being applied to a control gate of the storage transistors.

Claim 10

Method according to claim 1, which comprises shifting a threshold voltage of the storage transistors simultaneously in one direction for all storage addresses and successively in the other direction, when programming.

Claim 11

Method according to claim 9, which comprises carrying out the shifting step word by word.

Claim 12

Method according to claim 9, which comprises simultaneiously shifting the threshold voltage of the storage transistors for all storage addresses, when reprogramming.

Claim 13

Method according to claim 9, which comprises serially shifting the threshold voltage of the storage transistors by word for erasing and writing.

Claim 14

Apparatus for functionally testing a memory being electrically reprogrammable word by word, having storage cells being disposed in rows, each storage cell having a storage transistor, comprising an addressing circuit for addressing said storage transistors, means responsive to said addressing circuit for erasing information and writing information into the respective storage cell; means for varying the erasing or writing time for each of said storage cells; and control means for determining the limit of successful function in at least one of a predetermined erasing and writing state of at least one storage cell, and means responsive to said control means for terminating the erasing and writing times when the limit of said successful function has been determined by said control means.

Claim 15

Apparatus for functionally testing a memory being electrically reprogrammable word by word, having storage cells being disposed in rows, each storage cell having a storage transistor, comprising an addressing circuit for addressing said storage transistors, means responsive to said addressing circuit for erasing information and writing information into the respective storage cell; means for varying the erasing or writing time for each of said storage cells; and control means for determining the limit of successful function in at least one of a predetermined erasing and writing state of at least one storage cell, and means responsive to said control means for terminating the erasing and writing times when the limit of said successful function has been determined by said control means.