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US4755890A Expired / Lapsed US ⏱️ 0.0 years remaining

Channel filter

Assignee: Maxtor Corp
•
Filing: 1987-02-03
•
Granted: 1988-07-05
•
Expires: 2007-02-03
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Abstract

Abstract A channel filter employing time domain targeting techniques to eliminate inter symbol interference in the reading of information from magnetic media. A pulse detector outputs a signal characteristic of polarity reversals on the surface of magnetic storage media. This output signal is coupled to a tapped delay line network and a moderate order L-C network. The tapped delay line provides an output signal to the L-C network, which flattens out pre-cursive and post-cursive undershoots. As a result, a moderate order L-C network is sufficient to approximate the desired target response so that maximum information density can be achieved. The tapped delay line provides an output signal that consists of a superposition (sum) of the input signal delayed and weighted. This forms a transversal filter. As with any linear filter, reciprocity applies. Consequently, the output of the tapped delay line is taken from the input with AC coupling directly to ground. The output is taken from a low characteristic impedence, eliminating the need for an internal amplifier capable of driving a low impedence equal to the characteristic impedence of the delay line.

Inventors

  • 👤 Don Huber

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 21:35
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B20/10046

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 142 words
A circuit for detecting amplitude peaks of an input signal and for shaping said signal to a desired output signal, said circuit comprising: pulse detection means coupled to said input signal for detecting said amplitude peaks and for outputting a first differentiated output signal; tapped delay means coupled to said first output signal, said tapped delay means providing a second differentiated output signal, said second output signal taken from an input of said tapped delay means at the characteristic impedence of said tapped delay means; delay equalization means coupled to said second output signal; amplitude attenuation means coupled to said delay equalization means, said amplitude attenuation means outputting a third differentiated output signal; said third output signal coupled to differentiator means, said differentiator means outputting the derivative of said third output signal; detecting means for detecting zero crossing points of said derivative.
Claim 2
Dependent Claim 142 words
A circuit for detecting amplitude peaks of an input signal and for shaping said signal to a desired output signal, said circuit comprising: pulse detection means coupled to said input signal for detecting said amplitude peaks and for outputting a first differentiated output signal; tapped delay means coupled to said first output signal, said tapped delay means providing a second differentiated output signal, said second output signal taken from an input of said tapped delay means at the characteristic impedence of said tapped delay means; delay equalization means coupled to said second output signal; amplitude attenuation means coupled to said delay equalization means, said amplitude attenuation means outputting a third differentiated output signal; said third output signal coupled to differentiator means, said differentiator means outputting the derivative of said third output signal; detecting means for detecting zero crossing points of said derivative.
Claim 3
Dependent Claim 21 words
The circuit of claim 1 wherein said delay equalization means comprises first and second capacitors cross-coupled to said second output signal.
Claim 4
Dependent Claim 18 words
The circuit of claim 1 wherein said amplitude attenuation means comprises a ladder filter comprising inductors and capacitors.
Claim 5
Dependent Claim 15 words
The circuit of claim 1 further including amplifying means for amplifying said second output signal.
Claim 6
Dependent Claim 15 words
The circuit of claim 1 further including amplifying means for amplifying said third output signal.
Claim 7
Dependent Claim 42 words
The circuit of claim 1 wherein said first output signal is coupled to said tapped delay means through a pair of buses, said tapped delay means having a plurality of taps, each of said taps coupled to said buses through a resistor.
Claim 8
Dependent Claim 29 words
The circuit of claim 6 wherein the relative values of said resistors are determined by performing an iterative computation until said third output signal approximates said desired output signal.

References Cited (Backward Citations)

US4264935A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-07-05 1992-01-04 1992-07-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-07-05 1996-01-04 1996-07-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-07-05 2000-01-04 2000-07-05 $7700.00 Window Closed / Lapsed

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