US4755771A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Equalizing circuit
Assignee: Oki Electric Industry Co Ltd
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Filing: 1987-03-06
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Granted: 1988-07-05
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Expires: 2007-03-06
Abstract
Abstract An equalizer circuit for equalizing a signal attenuated in frequency while the same is transmitted through a transmission line and eliminates out-band high frequency noise so as to provide a signal having flat frequency characteristics. The equalizing circuit includes a high-pass circuit, a Sallen-Key low-pass circuit capable of gain regulation, constructed by connecting the output terminal of an operational amplifier through a resistance to the negative input terminal of the same and grounding the negative input terminal through a variable resistance, an amplifying circuit capable of gain control for amplifying a signal supplied to the positive input terminal of the operational amplifier of the Sallen-Key low-pass circuit, and a control circuit which detects the peak level of the output signal of the amplifying circuit and controls the resistance of the variable resistance of the Sallen-Key low-pass circuit and the gain of the amplifying circuit on the basis of the result of the detection.
Inventors
- 👤 Yousuke Sakaida
- 👤 Harutomo Narita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:20
CPC Classifications
H; H03; H03G; H03G5/00; H03G5/16; H03G5/165
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
173 words
An equalizing circuit for correcting frequency characteristics of input signals, said input signals being transmitted through a transmission circuit, said equalizing circuit comprising: a high-pass circuit connected to said transmission circuit for correcting said frequency characteristics of said input signals; a Sallen-Key low-pass circuit connected to said high-pass circuit, said Sallen-Key low-pass circuit having a first amplifying means, including a means for gain regulation thereof, for amplifying a signal from said high-pass circuit; a second amplifying means connected to an input terminal of said first amplifying means for amplifying a signal supplied to an input terminal thereof, said amplifying means including a means for gain regulation thereof; a control circuit connected to an output terminal of said second amplifying means for detecting the peak level of an output signal of said second amplifying means and for providing an output corresponding thereto, said control circuit output connected to both of said means for gain regulation, thereby controlling the gain of said first and second amplifying means on the basis of the detected peak level.
Claim 2
Dependent Claim
173 words
An equalizing circuit for correcting frequency characteristics of input signals, said input signals being transmitted through a transmission circuit, said equalizing circuit comprising: a high-pass circuit connected to said transmission circuit for correcting said frequency characteristics of said input signals; a Sallen-Key low-pass circuit connected to said high-pass circuit, said Sallen-Key low-pass circuit having a first amplifying means, including a means for gain regulation thereof, for amplifying a signal from said high-pass circuit; a second amplifying means connected to an input terminal of said first amplifying means for amplifying a signal supplied to an input terminal thereof, said amplifying means including a means for gain regulation thereof; a control circuit connected to an output terminal of said second amplifying means for detecting the peak level of an output signal of said second amplifying means and for providing an output corresponding thereto, said control circuit output connected to both of said means for gain regulation, thereby controlling the gain of said first and second amplifying means on the basis of the detected peak level.
Claim 3
Dependent Claim
24 words
An equalizing circuit as recited in claim 1, wherein said first amplifying means has a high impedance input impedance and a low output impedance.
Claim 4
Dependent Claim
23 words
An equalizing circuit as recited in claim 1, wherein said second amplifying means has a high input impedance and a low output impedance.
Claim 5
Dependent Claim
61 words
An equalizing circuit as recited in claim 1, wherein said first amplifying means has an operational amplifier, a resistance and a variable resistance, an output terminal of said operational amplifier being connected to a negative input terminal thereof through said resistance, said negative input terminal being grounded through said variable resistance, whereby said Sallen-Key low-pass circuit effects a gain regulation thereof.
Claim 6
Dependent Claim
90 words
An equalizing circuit as recited in claim 4, wherein said Sallen-Key low-pass circuit has a first resistance, a second resistance, a first capacitor and a second capacitor, one terminal of said first resistance being connected to said high-pass circuit, another terminal of said first resistance being connected to a positive input terminal of said operational amplifier through said second resistance and, further, being connected to an output terminal of said operational amplifier through said first capacitor, said positive input terminal of said operational amplifier being grounded through said second capacitor.
Claim 7
Dependent Claim
47 words
An equalizing circuit as recited in claim 1, wherein said second amplifying means has a variable resistance, an output terminal of said second amplifying means being connected to an input terminal thereof through said second variable resistance, whereby said second amplifying means effects a gain regulation thereof.
Claim 8
Dependent Claim
17 words
An equalizing circuit as recited in claim 1, wherein said control circuit is a peak detecting circuit.
Claim 9
Dependent Claim
229 words
An equalizing circuit for correcting frequency characteristics of input signals,said input signals being transmitted through a transmission circuit, said equalizing circuit comprising: a high-pass circuit connected to said transmission circuit for correcting said frequency characteristics of said input signals; a Sallen-Key low-pass circuit connected to said high-pass circuit, said Sallen-Key low-pass circuit having an operational amplifier, a resistance and a first variable resistance, the output terminal of said operational amplifier being connected to a negative input terminal thereof through said resistance, said negative input terminal being grounded through said first variable resistance, whereby said Sallen-Key low-pass circuit effects a gain regulation thereof; an amplifying circuit connected to a positive input terminal of said operational amplifier for amplifying a signal supplied to said positive input terminal of said operational amplifier, said amplifying circuit having a second variable resistance, an output terminal of said amplifying circuit being connected to an input terminal thereof through said second variable resistance, whereby said amplifying circuit effects a gain regulation thereof; a control circuit connected to an output terminal of said amplifying circuit for detecting the peak level of an output signal of said amplifying circuit and for providing an output signal corresponding thereto, said output signal of said control circuit controlling the value of said first variable resistance and the value of said second variable resistance on the basis of the detected peak level.
Claim 10
Dependent Claim
229 words
An equalizing circuit for correcting frequency characteristics of input signals,said input signals being transmitted through a transmission circuit, said equalizing circuit comprising: a high-pass circuit connected to said transmission circuit for correcting said frequency characteristics of said input signals; a Sallen-Key low-pass circuit connected to said high-pass circuit, said Sallen-Key low-pass circuit having an operational amplifier, a resistance and a first variable resistance, the output terminal of said operational amplifier being connected to a negative input terminal thereof through said resistance, said negative input terminal being grounded through said first variable resistance, whereby said Sallen-Key low-pass circuit effects a gain regulation thereof; an amplifying circuit connected to a positive input terminal of said operational amplifier for amplifying a signal supplied to said positive input terminal of said operational amplifier, said amplifying circuit having a second variable resistance, an output terminal of said amplifying circuit being connected to an input terminal thereof through said second variable resistance, whereby said amplifying circuit effects a gain regulation thereof; a control circuit connected to an output terminal of said amplifying circuit for detecting the peak level of an output signal of said amplifying circuit and for providing an output signal corresponding thereto, said output signal of said control circuit controlling the value of said first variable resistance and the value of said second variable resistance on the basis of the detected peak level.
Claim 11
Dependent Claim
90 words
An equalizing circuit as recited in claim 8, wherein said Sallen-Key low-pass circuit has a first resistance, a second resistance, a first capacitor and a second capacitor, one terminal of said first resistance being connected to said high-pass circuit, another terminal of said first resistance being connected to said positive input terminal of said operational amplifier through said second resistance and, further, being connected to an output terminal of said operational amplifier through said first capacitor, said positive input terminal of said operational amplifier being grounded through said second capacitor.
Claim 12
Dependent Claim
17 words
An equalizing circuit as recited in claim 8, wherein said control circuit is a peak detecting circuit.
References Cited (Backward Citations)
JPS6041332A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-05 | 1992-01-04 | 1992-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-05 | 1996-01-04 | 1996-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-05 | 2000-01-04 | 2000-07-05 | $7700.00 | Window Closed / Lapsed |