Patent US4493286A successfully refreshed from Google Patents.
US4754366A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Decoupling capacitor for leadless surface mounted chip carrier
Assignee: Circuit Components Inc
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Filing: 1987-03-19
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Granted: 1988-06-28
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Expires: 2007-03-19
Abstract
Abstract High frequency noise is decoupled from power supplied to a surface mounted integrated circuit (IC) leadless chip carrier package by installation of a surface mounted decoupling capacitor over the IC chip carrier package and printed circuit board. The decoupling capacitor comprises a dielectric material sandwiched between a pair of conductors and having a plurality of leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit over a surface mounted integrated circuit (IC) leadless chip carrier package and correspond to the power and ground pin configuration of that package.
Inventors
- 👤 Jorge M. Hernandez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 00:56
CPC Classifications
H; H01; H01G; H01G4/00; H01G4/002; H01G4/228; H01G2/00; H01G2/12; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0216; H05K1/023; H05K1/0231; H05K1/18; H05K2201/00; H05K2201/10; H05K2201/10431; H05K2201/10507; H05K2201/10515; H05K2201/10613; H05K2201/10621; H05K2201/10704; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/3447
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
241 words
A decoupling capacitor for use with a leadless surface mounted integrated circuit chip carrier package, the leadless chip carrier adapted for mounting on a circuit board and having an array of conductive connecting means arranged exteriorly on the perimeter thereof, at least some of the connecting means being first and second voltage level connecting means, the capacitor including: a flat dielectric body having a pair of opposed surfaces; a first conductor on one of said opposed surfaces of said dielectric body defining a first voltage level conductor; a second conductor on the other of the said opposed surfaces of said dielectric body defining a second voltage level conductor; a plurality of first leads in a predetermined configuration in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in a predetermined configuration in electrical contact with said second conductor and extending outwardly therefrom; the configurations of said first and second leads corresponding to configurations of first and second voltage levels of said connecting means of said leadless chip carrier package; an insulating material surrounding said dielectric body and conductors, said first and second leads extending though said insulating material; an said dielectric body, first conductor, second conductor and insulating material defining an insulated assembly, said plurality of first and second leads having a length and configuration to effect electrical contact with a circuit board when said insulated assembly is mounted over the leadless chip carrier package.
Claim 2
Dependent Claim
241 words
A decoupling capacitor for use with a leadless surface mounted integrated circuit chip carrier package, the leadless chip carrier adapted for mounting on a circuit board and having an array of conductive connecting means arranged exteriorly on the perimeter thereof, at least some of the connecting means being first and second voltage level connecting means, the capacitor including: a flat dielectric body having a pair of opposed surfaces; a first conductor on one of said opposed surfaces of said dielectric body defining a first voltage level conductor; a second conductor on the other of the said opposed surfaces of said dielectric body defining a second voltage level conductor; a plurality of first leads in a predetermined configuration in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in a predetermined configuration in electrical contact with said second conductor and extending outwardly therefrom; the configurations of said first and second leads corresponding to configurations of first and second voltage levels of said connecting means of said leadless chip carrier package; an insulating material surrounding said dielectric body and conductors, said first and second leads extending though said insulating material; an said dielectric body, first conductor, second conductor and insulating material defining an insulated assembly, said plurality of first and second leads having a length and configuration to effect electrical contact with a circuit board when said insulated assembly is mounted over the leadless chip carrier package.
Claim 3
Dependent Claim
12 words
The capacitor of claim 1 wherein: said insulated assembly is substantially rectangular.
Claim 4
Dependent Claim
12 words
The capacitor of claim 2 wherein: said insulated assembly is substantially square.
Claim 5
Dependent Claim
29 words
The capacitor of claim 1 wherein said dielectric body includes: a pair of metallized layers on said opposed surfaces thereof, said metallized layers contacting said first or second conductors.
Claim 6
Dependent Claim
17 words
The capacitor of claim 1 wherein: said dielectric body is bonded to said first and second conductors.
Claim 7
Dependent Claim
22 words
The capacitor of claim 1 wherein: said first and second leads terminate as flattened configurations for surface mounting on a circuit board.
Claim 8
Dependent Claim
17 words
The subassembly of claim 6 wherein; said dielectric body is bonded to said first and second conductors.
Claim 9
Dependent Claim
271 words
An electronic subassembly comprising: a leadless surface mounted integrated circuit chip carrier package, said chip carrier package adapted for surface mounting on a circuit board and having an array of conductive connecting means arranged exteriorly on the perimeter thereof, at least some of the connecting means being first and second voltage level connecting means; a circuit board, said circuit board having first spaced surface pads receiving said leadless chip carrier package connecting means; decoupling capacitor means, said decoupling capacitor means being aligned with and mounted over said chip carrier package and electrically communicating with said first spaced surface pads of said circuit board, said capacitor means comprising; a flat dielectric body having a pair of opposed surfaces; a first conductor on one of said opposed surfaces of said dielectric body defining a first voltage level conductor; a second conductor on the other of the said opposed surfaces of said dielectric body defining a second voltage level conductor; a plurality of first leads in a predetermined configuration in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in a predetermined configuration in electrical contact with said second conductor and extending outwardly therefrom; the configurations of said first and second leads corresponding to configurations of first and second voltage levels of said connecting means of said leadless chip carrier package; and said dielectric body, first conductor, second conductor and insulating material defining an insulated assembly, said plurality of first and second leads having a length and configuration to effect electrical contact with a circuit board when said insulated assembly is mounted over the leadless chip carrier package.
Claim 10
Dependent Claim
271 words
An electronic subassembly comprising: a leadless surface mounted integrated circuit chip carrier package, said chip carrier package adapted for surface mounting on a circuit board and having an array of conductive connecting means arranged exteriorly on the perimeter thereof, at least some of the connecting means being first and second voltage level connecting means; a circuit board, said circuit board having first spaced surface pads receiving said leadless chip carrier package connecting means; decoupling capacitor means, said decoupling capacitor means being aligned with and mounted over said chip carrier package and electrically communicating with said first spaced surface pads of said circuit board, said capacitor means comprising; a flat dielectric body having a pair of opposed surfaces; a first conductor on one of said opposed surfaces of said dielectric body defining a first voltage level conductor; a second conductor on the other of the said opposed surfaces of said dielectric body defining a second voltage level conductor; a plurality of first leads in a predetermined configuration in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in a predetermined configuration in electrical contact with said second conductor and extending outwardly therefrom; the configurations of said first and second leads corresponding to configurations of first and second voltage levels of said connecting means of said leadless chip carrier package; and said dielectric body, first conductor, second conductor and insulating material defining an insulated assembly, said plurality of first and second leads having a length and configuration to effect electrical contact with a circuit board when said insulated assembly is mounted over the leadless chip carrier package.
Claim 11
Dependent Claim
12 words
The subassembly of claim 8 wherein: said insulated assembly is substantially rectangular.
Claim 12
Dependent Claim
12 words
The subassembly of claim 8 wherein: said insulated assembly is substantially square.
Claim 13
Dependent Claim
27 words
The subassembly of claim 8 wherein said first spaced sufface pads include: pad extensions for receiving said first and second voltage level leads of said decoupling capacitor.
Claim 14
Dependent Claim
29 words
The subassembly of claim 8 wherein said dielectric body includes: a pair of metallized layers on said opposed surfaces thereof, said metallized layers contacting said first or second conductors.
Claim 15
Dependent Claim
22 words
The subassembly of claim 8 wherein: said first and second leads terminate as flattened configurations for surface mounting on a circuit board.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-28 | 1991-12-28 | 1992-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-28 | 1995-12-28 | 1996-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-28 | 1999-12-28 | 2000-06-28 | $7700.00 | Window Closed / Lapsed |