Method and apparatus for qualifying the decode window margin of a phase locked loop data synchronizer

Claim 3

The method according to claim 1 wherein a static moveable test bit scheme is used to shift the test bit's time position about an expected decode window position.

Claim 4

The method according to claim 2 wherein the moveable bit is mechanized by a linear ramp threshold generator to trigger a monostable multivibrator for delay or shift of the test bit's time position.

Claim 5

The method according to claim 1 wherein the test vectors and code patterns are embedded in a read only memory asynchronously clocked to the PLL inputs.

Claim 6

The method according to claim 1 wherein the number of read gate cycles and the correctly decoded moveable test bit, the synchronized data pulse, form a ratio output indication signal for accurately monitoring the proper decoding of a test bit to qualify the performance margins of the PLL.

Claim 7

A phase locked loop test apparatus comprising: (a) a first oscillator which generates a synchronous clock signal; (b) a counter which is stepped by the synchronous clock signal and generates an output comprising sequential addresses; (c) a read-only-memory (ROM) which stores a plurality of test patterns and serially outputs individual test patterns in response to addresses received from the counter; (d) a second oscillator which generates a crystal reference clock which is provided to a PLL device under test; (e) an adjustable ramp rate generator which receives a test bit signal from the ROM, the ramp generator including a potentiometer which can be adjusted to vary the timing of the data test bit signal; (f) a mono-stable multivibrator which receives the adjusted data test bit signal and generates a required pulse width of the data test bit appropriate for the data rate under investigation; (g) an OR gate which receives a periodic test pattern from the ROM and the adjusted data test bit signal from the mono-stable multivibrator and provides a composite encoded data signal as an output; (h) a flip-flop which receives a control signal from the ROM and the output signal of the PLL's VCO and provides an output signal representing a window of observation for the moveable test bit; and (i) a second OR gate which receives the synchronized output data of the PLL device under test and the observation window signal from the flip-flop and provides a ratio out signal which is indicative of whether the data test bit is within or outside of its expected window boundary.

Claim 8

A phase locked loop test apparatus comprising: (a) a first oscillator which generates a synchronous clock signal; (b) a counter which is stepped by the synchronous clock signal and generates an output comprising sequential addresses; (c) a read-only-memory (ROM) which stores a plurality of test patterns and serially outputs individual test patterns in response to addresses received from the counter; (d) a second oscillator which generates a crystal reference clock which is provided to a PLL device under test; (e) an adjustable ramp rate generator which receives a test bit signal from the ROM, the ramp generator including a potentiometer which can be adjusted to vary the timing of the data test bit signal; (f) a mono-stable multivibrator which receives the adjusted data test bit signal and generates a required pulse width of the data test bit appropriate for the data rate under investigation; (g) an OR gate which receives a periodic test pattern from the ROM and the adjusted data test bit signal from the mono-stable multivibrator and provides a composite encoded data signal as an output; (h) a flip-flop which receives a control signal from the ROM and the output signal of the PLL's VCO and provides an output signal representing a window of observation for the moveable test bit; and (i) a second OR gate which receives the synchronized output data of the PLL device under test and the observation window signal from the flip-flop and provides a ratio out signal which is indicative of whether the data test bit is within or outside of its expected window boundary.

Claim 9

The apparatus according to claim 6 wherein the test vector and test patterns are coded in the high speed registered memory cell array which contains specially arranged sync and reference pulses and appropriate digital patterns for control and encoded data inputs to the PLL DUT.

Claim 10

The apparatus according to claim 6 wherein a synchronized data bit window is generated for accurate monitoring of when mis-decode of the test bit occurs.

Claim 11

The apparatus according to claim 6 wherein an adjustable ramp rate generator comprising an emitter-follower and a RC network, together with a mono-stable multivibrator with adjustable pulse width are employed to generate a suitable moveable test bit for any data rate of interest on the PLL DUT thereby eliminating the need for expensive tapped delay lines and providing continuous delay variation.

Claim 12

The apparatus according to claim 6 wherein two crystal resonator controlled, modified pierce-type gate oscillators are used for the 2F reference clock and for the system clock.