Sequence control system employing a plurality of programmable logic controllers

Claim 2

A sequence control system employing a plurality of programmable logic controllers for performing sequence control in accordance with a ladder diagram, said programmable logic controllers being linkedly coupled by data transfer means for transferring data among said programmable logic controllers, each said controller being available to independently perform individual sequence control in accordance with its ladder diagram and capable of exchanging data necessary to perform said sequence control, each said programmable logic controller comprising: user program memory means for storing a user program which causes said sequence control to be performed, said sequence control using an address of an external programmable logic controller; I/O circuitry means, including input means for receiving an input control signal from an external device and output means for sending an output control signal to an external device, said output control signal indicative of a sequence control to be performed in said external device; system memory means for storing first data from said input control signal received by said I/O circuitry means in an external data area, and for storing second data in an internal data area; CPU means, coupled to said system memory means, for successively executing instructions of said user program stored in said user program memory means to process said first data based on arithmetic operations with said second data to produce processed data, and for writing said processed data into said system memory means as revised output data which corresponds to said output control signal; I/O interface means, coupled to said I/O circuitry means and said system memory means, for writing said input control signal into said external data area of said system memory means so as to revise data stored in external data area of said system memory means; and for setting output data stored in said external data area of said system memory means in said output means of said I/O circuitry means, said output data corresponding to said output control signal; address table memory means for storing address data designating an address in said system memory means so as to write input data thereto and read out output data therefrom; wherein said system memory means has an address space adequate to store input/output data corresponding to said plurality of linkedly connected programmable logic controllers, said address space having said internal data area, which is a field for intra-equipment, and said external data area, which is another field for at least one extra-equipment; wherein said CPU mean includes: (a) means for determining said address of said external programmable logic controller used by the user program of said user program memory means and for storing said address used in said extra-equipment field in said address table memory means in accordance with an initializing process performed prior to executing said user program; (b) means for sending said address used said extra-equipment field through said data transfer means; (c) means for receiving an input/output address from said extra-equipment and for storing said input/output address in said address table memory means; (d) means for controlling a writing of said input control signal into said external data area of said system memory means and for controlling a transferring of said output data from said external data area of said system memory means to said I/O circuitry means; and (e) means for exchanging data addressed by said input/output address through said data transfer means to said extra-equipment and receiving corresponding data from said intra-equipment.

Claim 3

The sequence control system according to claim 1 wherein said CPU means includes means for successively executing the user program in said programmable logic controller while exchanging said data between said intra-equipment and any of said extra-equipment.

Claim 4

The sequence control system according to claim 2 wherein said CPU means includes means for holding a waiting status to perform auxiliary operations until its successive execution because of an execution of any of said extra-equipment linked to said intra-equipment.

Claim 5

A sequence control system employing a plurality of programmable logic controllers for performing sequence control in accordance with a ladder diagram, said programmable logic controllers being linkedly coupled by data transfer means for transferring data among said programmable logic controllers, each said controller being available to independently perform individual sequence control in accordance with its ladder diagram and capable of exchanging data necessary to perform said complicated sequence control, each said programmable logic controller comprising: user program memory means for storing a user program which causes said sequence control to be performed, said sequence control using an address of an external programmable logic controller; I/O circuitry means, including input means for receiving an input control signal from an external device and output means for sending an output control signal to an external device, said output control signal indicative of a sequence control to be performed in the external device; system memory means for storing first data from said input control signal received by said I/O circuitry means in an external data area and for storing second data in an internal data area; CPU means, coupled to said system memory means, for successively executing instructions of said user program stored in said user program memory means to process said first data based on arithmetic operations with said second data to produce processed data, and for writing said processed into said system memory means as revised output data which corresponds to said output control signal; I/O interface means, coupled to said I/O circuitry means and said system memory means, for writing said input control signal into said external data area of said system memory means so as to revise data stored in external data area of said system memory means, and for setting output data stored in said external data area of said system memory means in said output means of said I/O circuitry means, said output data corresponding to said output control signal; address table memory means for storing address data designating an address in said system memory means so as to write input data and read out output data; wherein said system memory means has an address space adequate to store input/output data corresponding to said plurality of linkedly connected programmable logic controllers, said address space having said internal data area which is a field for intra-equipment, and said external data area which is another field for at least one extra-equipment; wherein said CPU means includes: (a) means for determining said address of said external programmable logic controller used by the user program of said user program memory means and for storing said address used in said extra-equipment field in said address table memory means in accordance with an initializing process performed prior to executing said user program; (b) means for sending said address used said extra-equipment field through said data transfer means; (c) means for receiving an input/output address from said extra-equipment and for storing said input/output address into said address table memory means; (d) means for controlling a writing said input control signal into said external data area of said system memory means and for controlling a transferring of said output data from said external data area of said system memory means to said I/O circuitry means; and (e) means for exchanging data addressed by said input/output address through said data transfer means to said extra equipment and receiving corresponding data from said intra-equipment; and (f) means for synchronizing operations between said intra-equipment and said extra-equipment.

Claim 6

A sequence control system employing a plurality of programmable logic controllers for performing sequence control in accordance with a ladder diagram, said programmable logic controllers being linkedly coupled by data transfer means for transferring data among said programmable logic controllers, each said controller being available to independently perform individual sequence control in accordance with its ladder diagram and capable of exchanging data necessary to perform said complicated sequence control, each said programmable logic controller comprising: user program memory means for storing a user program which causes said sequence control to be performed, said sequence control using an address of an external programmable logic controller; I/O circuitry means, including input means for receiving an input control signal from an external device and output means for sending an output control signal to an external device, said output control signal indicative of a sequence control to be performed in the external device; system memory means for storing first data from said input control signal received by said I/O circuitry means in an external data area and for storing second data in an internal data area; CPU means, coupled to said system memory means, for successively executing instructions of said user program stored in said user program memory means to process said first data based on arithmetic operations with said second data to produce processed data, and for writing said processed into said system memory means as revised output data which corresponds to said output control signal; I/O interface means, coupled to said I/O circuitry means and said system memory means, for writing said input control signal into said external data area of said system memory means so as to revise data stored in external data area of said system memory means, and for setting output data stored in said external data area of said system memory means in said output means of said I/O circuitry means, said output data corresponding to said output control signal; address table memory means for storing address data designating an address in said system memory means so as to write input data and read out output data; wherein said system memory means has an address space adequate to store input/output data corresponding to said plurality of linkedly connected programmable logic controllers, said address space having said internal data area which is a field for intra-equipment, and said external data area which is another field for at least one extra-equipment; wherein said CPU means includes: (a) means for determining said address of said external programmable logic controller used by the user program of said user program memory means and for storing said address used in said extra-equipment field in said address table memory means in accordance with an initializing process performed prior to executing said user program; (b) means for sending said address used said extra-equipment field through said data transfer means; (c) means for receiving an input/output address from said extra-equipment and for storing said input/output address into said address table memory means; (d) means for controlling a writing said input control signal into said external data area of said system memory means and for controlling a transferring of said output data from said external data area of said system memory means to said I/O circuitry means; and (e) means for exchanging data addressed by said input/output address through said data transfer means to said extra equipment and receiving corresponding data from said intra-equipment; and (f) means for synchronizing operations between said intra-equipment and said extra-equipment.

Claim 7

The programmable logic controller according to claim 4 further comprising means for selecting an operation mode of said controller.

Claim 8

The programmable logic controller according to claim 5 wherein said selecting means selects operation modes which correspond to one of a sequence control operation within said controller or another sequence control operation between a plurality of programmable logic controllers.

Claim 9

The programmable logic controller according to claim 4 which further comprises means for determining an equipment number data of said controller so as to identify said controller when a plurality of programmable logic controllers are linkedly connected.

Claim 10

The programmable logic controller according to claim 7 wherein said means for determining includes a settable switch which can be set between different equipment numbers.

Claim 11

The programmable logic controller according to claim 4 further comprising preset means for determining whether said controller will act as a master equipment in order to dominate other programmable logic controllers that are linkedly connected thereto.

Claim 12

The programmable logic controller according to claim 9 wherein said preset means includes a switch.