Digital signal processing system and method

Claim 1

A digital signal processing system for generating read-enable pulses comprising: a record medium for storing digital data; first means for reproducing a first signal representative of said stored ditigal data and which has a signal level varying according to the stored digital data; second means for monitoring said first signal and upon detecting a peak in said first signal, producing a read-enable pulse; and third means, cooperative with said second means, for monitoring said first signal level and enabling said second means to produce said read-enable pulses every time said first signal level crosses a predetermined threshold level, said third means being responsive to said second means producing said read-enable pulse to subsequently disable said second means until the next time said first signal level crosses said predetermined threshold level; wherein: said second means comprises a differentiation circuit for producing a second signal indicative of the differentiated value of said first signal and a first detector means which produces a read-enable pulse upon detecting zero-crossing of said second signal; said first detector means is enabled and disabled by said third means; said third means comprises a second detector means having a second comparator continuously comparing said first signal level with said predetermined threshold level and enabling said second means to produce said read-enable pulse when said first detector means detects zero-crossing of said second signal; said third means is disabled when said second means produces said read-enable signal until said second comparator detects that said first signal level has again crossed said predetermined threshold level; said predetermined threshold level comprises a first positive threshold level and a second negative threshold level, and said second comparator switches its output level between HIGH and LOW levels each time said first signal level moves outside the range defined by said first and second threshold levels; said second detector further comprises an enable signal generator for producing an enable signal enabling said second means at every occurrence of switching of said second comparator output level; said first detector comprises a first comparator which switches its output level between HIGH and LOW levels at every occurrence of positive-going and negative-going zero-crossings of said second signal, and wherein said second means produces said read-enable pulse in response to every occurrence of switching of said first comparator output in the presence of said enable signal from said third means; and said enable signal generator comprises a first enable signal generator responsive to switching of said second comparator output from LOW level to HIGH level to produce said enable signal, and a second enabling signal gnerator responsive to switching of said second comparator output from HIGH level to LOW level to produce said enable signal, and wherein said enable signal from one of said first and second enable signal generators is transmitted to said second means through a second OR gate.