Geometric arrangement for filter capacitors

Claim 2

A circuit arrangement for capacitors comprising: (a) a first group of N capacitors wherein N is greater than one, each of said N capacitors having first and second terminals; (b) first and second connection points; (c) third and fourth connection points; (d) first means for electrically connecting said first and said second terminals of each of said N capacitors to said first and said second connection points, respectively, such that all of said first and said second terminals are electrically equidistant from said first and said second connection points, said first means providing an inductor in each of said first means electrical connections, said first means electrical connections being physically arranged so that each of said inductors have essentially the same predetermined inductance and said electrical connections are not coupled to each other; and (e) second means for electrically connecting said first and said second terminals of each of said N capacitors to said third and said fourth connection points, respectively, such that all of said first and said second terminals are electrically equidistant from said third and said fourth connection points, said second means providing an inductor in each of said second means electrical connections, said second means electrical connections being physically arranged so that said second means electrical connections for said first and said second terminals of each of said N capacitors are coupled to each other to thereby minimize the inductive effect in said inductors.

Claim 3

The circuit arrangement of claim 1 further comprising: (a) a second group of M capacitors wherein M is greater than one, each of said second group M capacitors having said first and said second terminals; (b) third means for electrically connecting said first and said second terminals of each of said second group M capacitors to said first and said second connection points, respectively, such that all of said first and said second terminals are electrically equidistant from said first and said second connection points, said third means providing an inductor in each of said third means electrical connections, said third means electrical connections being physically arranged so that each of said inductors have essentially the same predetermined inductance as said predetermined inductance of said first means provided inductors and said electrical connections are not coupled to each other; and (c) fourth means for electrically connecting said first and said second terminals of each of said second group M capacitors to said third and said fourth connection points, respectively, such that all of said first and said second terminals are electrically equidistant from said third and said fourth connection points, said fourth means providing an inductor in each of said fourth means electrical connections, said fourth means electrical connections being physically arranged so that said fourth means electrical connections for said first and said second terminals of each of said second group M capacitors are coupled to each other to thereby minimize the inductive effect of said inductors.

Claim 4

The circuit arrangement of claim 2 wherein M is equal to N.

Claim 5

The circuit arrangement of claim 1 further comprising: (a) M groups of N capacitors each wherein M is one or greater and N is greater than one, each of said M times N capacitors having said first and said second terminals; (b) first means associated with a respective one of each of said M groups for electrically connecting said first and said second terminals of each of said N capacitors in each of said associated groups to said first and said second connection points, respectively, said first means providing an inductor in each of said first associated means electrical connections, said first associated means electrical connections being physically arranged so that each of said inductors have essentially the same predetermined inductance as said predetermined inductance of said first means provided inductors and said electrical connections are not coupled to each other; and (c) second means associated with a respective one of each of said M groups for electrically connecting said first and said second terminals of each of said N capacitors in each of said associated groups to said third and said fourth connection points, respectively, said second associated means providing an inductor in each of said second associated means electrical connections, said second associated means electrical connections being physically arranged so that said second associated means electrical connections for said first and said second terminals of each of said N capacitors in each of said associated groups are coupled to each other to thereby minimize the inductive effect of said inductors.

Claim 6

The circuit arrangement of claim 1 wherein said first group of N capacitors are mounted on a printed circuit board having at least four layers; said first means are conductive traces on one layer of said at least four layers for electrically connecting said first terminals to said first connection points and are also conductive traces on another layer of said at least four layers for electrically connecting said second terminals to said second connection points; and said second means are conductive traces on yet another layer of said at least four layers for electrically connecting said first terminals to said third connection points and are also conductive traces on a remaining layer of said at least four layers for electrically connecting said second terminals to said fourth connection points.

Claim 7

The circuit arrangement of claim 5 wherein said printed circuit board has only four layers and said first group of N capacitors are mounted on either said one layer or said another layer of said four layers.

Claim 8

The circuit arrangement of claim 6 wherein said one layer and said another layer lie one on top of another; and said yet another layer and said remaining layer also lie one on top of another.

Claim 9

The circuit arrangement of claim 5 wherein said printed circuit board has only four layers and said first group of N capacitors are mounted either on said remaining layer or said yet another layer of said four layers.

Claim 10

The circuit arrangement of claim 8 wherein said one layer and said another layer lie one on top of another; and said yet another layer and said remaining layer also lie one on top of another.

Claim 11

A circuit arrangement for connecting two or more capacitors in parallel between two input points and two output points, each of said capacitors having first and second terminals, said arrangement comprising: (a) first means for electrically connecting said first terminal of each of said two or more capacitors to one of said input points and for electrically connecting said second terminal of each of said two or more capacitors to the other of said input points such that all of said first and said second terminals are electrically equidistant from said first and said connection points, said first means providing in each of said electrical connections an inductor, said first means electrical connections being physically arranged so that each of said inductors have essentially the same predetermined inductance and said electrical connections for said first and said second terminals of each of said two or more capacitors are not coupled to each other; and (b) second means for electrically connecting said first terminal of each of said two or more capacitors to one of said output points and for electrically connecting said second terminal of each of said two or more capacitors to the other of said output points such that all of said first and said second terminals are electrically equidistant from said third and said fourth connection points, said second means providing in each of said electrical connections an inductor, said second means electrical connections being physically arranged so that said second means electrical connections for said first and said second terminals of each of said two or more capacitors are coupled to each other to thereby minimize any inductive effect of said inductors.

Claim 12

A circuit arrangement for connecting two or more capacitors in parallel between two input points and two output points, each of said capacitors having first and second terminals, said arrangement comprising: (a) first means for electrically connecting said first terminal of each of said two or more capacitors to one of said input points and for electrically connecting said second terminal of each of said two or more capacitors to the other of said input points such that all of said first and said second terminals are electrically equidistant from said first and said connection points, said first means providing in each of said electrical connections an inductor, said first means electrical connections being physically arranged so that each of said inductors have essentially the same predetermined inductance and said electrical connections for said first and said second terminals of each of said two or more capacitors are not coupled to each other; and (b) second means for electrically connecting said first terminal of each of said two or more capacitors to one of said output points and for electrically connecting said second terminal of each of said two or more capacitors to the other of said output points such that all of said first and said second terminals are electrically equidistant from said third and said fourth connection points, said second means providing in each of said electrical connections an inductor, said second means electrical connections being physically arranged so that said second means electrical connections for said first and said second terminals of each of said two or more capacitors are coupled to each other to thereby minimize any inductive effect of said inductors.

Claim 13

The circuit arrangement of claim 10 wherein said each of said two or more capacitors are mounted on a printed circuit board having at least four layers; said first means are conductive traces on one layer of said at least four layers for electrically connecting said first terminals to said first connection points and are also conductive traces on another layer of said at least four layers for electrically connecting said second terminals to said second connection points; and said second means are conductive traces on yet another layer of said at least four layers for electrically connecting said first terminals to said third connection points and are also conductive traces on a remaining layer of said at least four layers for electrically connecting said second terminals to said fourth connection points.

Claim 14

The circuit arrangement of claim 11 wherein said printed circuit board has only four layers and each of said two or more capacitors are mounted on either said one layer or said another layer of said four layers.

Claim 15

The circuit arrangement of claim 12 wherein said one layer and said another layer lie one on top of another; and said yet another layer and said remaining layer also lie one on top of another.

Claim 16

The circuit arrangement of claim 11 wherein said printed circuit board has only four layers and each of said two or more capacitors are mounted either on said remaining layer or said yet another layer of said four layers.

Claim 17

The circuit arrangement of claim 14 wherein said one layer and said another layer lie one on top of another; and said yet another layer and said remaining layer also lie one on top of another.