Phase detector independent of clock duty-cycle

Claim 1

A phase detector for generating a measurement signal, after detection of a flank of a data pulse, which indicates the extent to which the actual distance (τ) between the flank of a data pulse, generated for serial data transmission, and the detection time, determined by a clock signal, differs from a required distance (Tg), and wherein the operation of the phase detector is independent of the duty-cycle of the clock signal, the phase detector comprising: (a) an exclusive OR-gate and a first D-flipflop controlled by a clock signal, the data pulse being fed to the D-input of the first D-flipflop and to a first input of the exclusive OR-gate while the output signal of the first D-flipflop functions as a detected data signal and is fed to a second input of the exclusive OR-gate to generate a detection signal at the output of the exclusive OR-gate; (b) a second D-flipflop for generating a reference signal whose pulse width is derived from the detection signal and is a measure of the required distance (Tg), having its D-input connected to the output of the exclusive OR-gate and its clock input directly connected to the clock input of the first D-flipflop; (c) an adjustment circuit connected to the output of the exclusive OR-gate for varying the amplitude of the detection signal such that the ratio between the amplitude of the reference signal and the amplitude of the adjusted detection signal is equal to Tg/T; and (d) a subtraction circuit connected to the adjustment circuit and the second D-flipflop for generating the measurement signal which represents the average value of the difference in amplitude between the adjusted detection signal and the reference signal.