US4748556A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Variable tracking word recognizer for detecting the occurrence of a dynamic-variable address
Assignee: Tektronix Inc
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Filing: 1985-05-28
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Granted: 1988-05-31
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Expires: 2005-05-28
Abstract
Abstract A variable tracking word recognizer generates an indicating signal when a microprocessor has accessed a memory stack location storing a dynamically addressed variable, the address of the variable being the sum of a dynamically assigned base address of the memory stack and a known address offset where the variable is stored on the stack in relation to the base address. The variable tracking word recognizer stores the dynamically assigned base address, when determined by a space allocation subroutine of a program running on the microprocessor, and then monitors the addresses subsequently appearing on the microprocessor address bus, generating the indicating signal when the current address matches the combination of stored base address and known address offset. The variable tracking word recognizer comprises circuitry to generate a storage control signal when the base address appears on the data bus of the microprocessor, a base register for storing the base address on occurrence of the storage control signal, an arithmetic logic unit for determining the difference between the number stored in the base register and each address appearing on the microprocessor address bus, and a conventional word recognizer to generate the indicating signal when the difference so generated equals the known offset.
Inventors
- 👤 Gerd H. Hoeren
- 👤 David D. Chapman
- 👤 Robin L. Teitzel
- 👤 Steven R. Palmquist
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:59
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/22; G06F11/25; G06F11/30; G06F11/34
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
199 words
An apparatus for determining when a program running on a processing device accesses a memory address of a dynamically addressed variable, the apparatus comprising: first means for determining when a base address occurs on a data bus associated with the processing device, the first means including second means for determining when a selected program step has occurred after which the base address is established, and third means for determining when the base address is being written to a base pointer address, such that the first means will output a signal upon the occurrence of an indication from the third means that occurs after an indication from the second means; means for storing the base address in a storage device when it occurs on the data bus, the means for storing being responsive to the signal from the first means for determining, and means for determining when a currently accessed memory address matches the sum of the stored base address and an offset number characterizing a relative address of the variable in relation to the base address and for generating a coincidence signal; whereby said coincidence signal indicates that a dynamically addressed variable has been addressed by said processing device.
Claim 2
Independent Claim
199 words
An apparatus for determining when a program running on a processing device accesses a memory address of a dynamically addressed variable, the apparatus comprising: first means for determining when a base address occurs on a data bus associated with the processing device, the first means including second means for determining when a selected program step has occurred after which the base address is established, and third means for determining when the base address is being written to a base pointer address, such that the first means will output a signal upon the occurrence of an indication from the third means that occurs after an indication from the second means; means for storing the base address in a storage device when it occurs on the data bus, the means for storing being responsive to the signal from the first means for determining, and means for determining when a currently accessed memory address matches the sum of the stored base address and an offset number characterizing a relative address of the variable in relation to the base address and for generating a coincidence signal; whereby said coincidence signal indicates that a dynamically addressed variable has been addressed by said processing device.
Claim 3
Dependent Claim
23 words
An apparatus as in claim 1 wherein said second means comprises a word recognizer coupled to monitor addresses occurring on an address bus.
Claim 4
Dependent Claim
41 words
An apparatus as in claim 1, wherein said third means comprises a word recognizer coupled to monitor addresses occurring on an address bus associated with the processing device and a signal indicating occurrence of a write operation in the processing device.
Claim 5
Independent Claim
164 words
An apparatus for determining when a program running on a processing device addresses a memory address of a dynamically addressed variable, the apparatus comprising: means for determining when a selected program step address occurs on an address bus, means for determining when a base pointer address occurs on the address bus during a processing device write cycle following an indication from the means for determining when a selected program step address occurs, means for storing the base address appearing on a data bus in a storage device in accordance with an indication from the means for determining when a base pointer address occurs, means for determining the difference between the stored base address and a currently accessed address, and means for comparing the difference to an offset number characterizing a relative address of the variable in relation to the base address and for generating a coincidence signal; whereby said coincidence signal indicates that a dynamically addressed variable has been addressed by said processing device.
Claim 6
Independent Claim
164 words
An apparatus for determining when a program running on a processing device addresses a memory address of a dynamically addressed variable, the apparatus comprising: means for determining when a selected program step address occurs on an address bus, means for determining when a base pointer address occurs on the address bus during a processing device write cycle following an indication from the means for determining when a selected program step address occurs, means for storing the base address appearing on a data bus in a storage device in accordance with an indication from the means for determining when a base pointer address occurs, means for determining the difference between the stored base address and a currently accessed address, and means for comparing the difference to an offset number characterizing a relative address of the variable in relation to the base address and for generating a coincidence signal; whereby said coincidence signal indicates that a dynamically addressed variable has been addressed by said processing device.
Claim 7
Independent Claim
177 words
An apparatus for generating a first indicating signal when a program running on a processing device accesses a memory address of a dynamically addressed variable, the apparatus comprising: a register for storing a base address occurring on a data bus of the processing device on occurrence of a fourth indicating signal, an arithmetic logic unit for determining the difference between a current address on an address bus of the processing device and the stored base address, a first word recognizer for generating the first indicating signal when said difference matches an address offset characterizing a relative address of the variable in relation to the base address, a second word recognizer for generating a second indicating signal when an address of a base address pointer appears on the address bus during a processing device write cycle, a third word recognizer for generating a third indicating signal when an address of a selected program step appears on the address bus, and a logic circuit for generating the fourth indicating signal on occurrence of the second and third indicating signals.
Claim 8
Independent Claim
177 words
An apparatus for generating a first indicating signal when a program running on a processing device accesses a memory address of a dynamically addressed variable, the apparatus comprising: a register for storing a base address occurring on a data bus of the processing device on occurrence of a fourth indicating signal, an arithmetic logic unit for determining the difference between a current address on an address bus of the processing device and the stored base address, a first word recognizer for generating the first indicating signal when said difference matches an address offset characterizing a relative address of the variable in relation to the base address, a second word recognizer for generating a second indicating signal when an address of a base address pointer appears on the address bus during a processing device write cycle, a third word recognizer for generating a third indicating signal when an address of a selected program step appears on the address bus, and a logic circuit for generating the fourth indicating signal on occurrence of the second and third indicating signals.
References Cited (Backward Citations)
US3906454A
Cited
US4048671A
Cited
US4166290A
Cited
US4338660A
Cited
US4434488A
Cited
US4495565A
Cited
US4636940A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-31 | 1991-11-30 | 1992-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-31 | 1995-11-30 | 1996-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-31 | 1999-11-30 | 2000-05-31 | $7700.00 | Window Closed / Lapsed |