US4748498A
Expired / Lapsed
US
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Luminance signal processing circuit with recursive filter for reducing noise while retaining a high vertical resolution
Assignee: Panasonic Holdings Corp
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Filing: 1986-11-17
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Granted: 1988-05-31
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Expires: 2006-11-17
Abstract
Abstract A luminance signal processing circuit includes a delay circuit for delaying a signal by one horizontal period, a first adder for adding an input signal and an output signal of the delay circuit, a filter circuit for passing a specified frequency band of an output of the first adder, a first coefficient circuit for multiplying an output of the filter circuit with a specified coefficient, a second adder for adding an output of the first coefficient circuit and the input signal to use the sum output signal as the input signal to the delay circuit, a subtracter for subtracting the output signal of the delay circuit from the input signal of the delay circuit, an amplitude limiter for limiting the amplitude of an output of the subtracter, and a second coefficient circuit for multiplying an output of the amplitude limter with a specified coefficient. An output signal of the second coefficient circuit is substracted from the input signal to reduce noise in the input signal, or added to the input signal to emphasize the input signal. In the presence of vertical correlation, this circuit acts as a comb filter with a varied passing range depending on frequency to effectively reduce visible noise. In the absence of vertical correlation, the output signal is hardly affected and the noise reduction is not effected, so that the vertical resolution is not lowered.
Inventors
- 👤 Kazuhiro Yamanishi
- 👤 Kouichi Igata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:15
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/21; H04N5/213; H04N5/76; H04N5/91; H04N5/911
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
186 words
A luminance signal processing circuit comprising: a delay circuit for delaying a signal by one horizontal period time; a first adder for adding an input signal and an output signal of said delay circuit; a filter circuit for passing a specified frequency band of an output signal of said first adder; a first coefficient circuit for multiplying an output of said filter circuit with a specified coefficient; a second adder for adding said input signal and an output of said first coefficient circuit to use the sum output signal as an input signal of said delay circuit; a subtracter for subtracting the output signal of said delay circuit from the input signal of said delay circuit; an amplitude limiter for limiting the amplitude of an output signal of said subtracter; a second coefficient circuit for multiplying an output of said amplitude limiter with a specified coefficient; and an operation circuit for calculating a sum or difference of an output signal of said second coefficient circuit and said input signal, an output signal of said operation circuit being an output signal of said luminance signal processing circuit.
Claim 2
Dependent Claim
186 words
A luminance signal processing circuit comprising: a delay circuit for delaying a signal by one horizontal period time; a first adder for adding an input signal and an output signal of said delay circuit; a filter circuit for passing a specified frequency band of an output signal of said first adder; a first coefficient circuit for multiplying an output of said filter circuit with a specified coefficient; a second adder for adding said input signal and an output of said first coefficient circuit to use the sum output signal as an input signal of said delay circuit; a subtracter for subtracting the output signal of said delay circuit from the input signal of said delay circuit; an amplitude limiter for limiting the amplitude of an output signal of said subtracter; a second coefficient circuit for multiplying an output of said amplitude limiter with a specified coefficient; and an operation circuit for calculating a sum or difference of an output signal of said second coefficient circuit and said input signal, an output signal of said operation circuit being an output signal of said luminance signal processing circuit.
Claim 3
Dependent Claim
17 words
A luminance signal processing circuit according to claim 1, wherein said filter circuit possesses a high-emphasis characteristic.
Claim 4
Dependent Claim
17 words
A luminance signal processing circuit according to claim 1, wherein said filter circuit possesses a band-emphasis characteristic.
Claim 5
Dependent Claim
28 words
A luminance signal processing circuit according to claim 1, wherein said operation circuit is a subtractor, whereby said luminance signal processing circuit reduces noise in said input signal.
Claim 6
Dependent Claim
26 words
A luminance signal processing circuit according to claim 1, wherein said operation circuit is an adder, whereby said luminance signal processing circuit emphasizes said input signal.
Claim 7
Dependent Claim
205 words
A luminance signal processing circuit comprising: an operation circuit for calculating a sum or difference of an input signal and another signal; a delay circuit for delaying a signal for one horizontal period; a first adder for adding an output signal of said operation circuit and an output signal of said delay circuit; a filter circuit for passing a specified frequency band of an output signal of said first adder; a first coefficient circuit for multiplying an output signal of said filter circuit with a specified coefficient; a second adder for adding the output signal of said operation circuit and an output signal of said coefficient circuit to use the sum output signal as an input signal to said delay circuit; a subtractor for subtracting the output signal of said delay circuit from the input signal of said delay circuit; an amplitude limiter for limiting the amplitude of an output signal of said subtractor; and a second coefficient circuit for multiplying an output of said amplitude limiter with a specified coefficient; an output signal of said second coefficient circuit being the another signal fed to said operation circuit, the output signal of said operation circuit being an output signal of said luminance signal processing circuit.
Claim 8
Dependent Claim
205 words
A luminance signal processing circuit comprising: an operation circuit for calculating a sum or difference of an input signal and another signal; a delay circuit for delaying a signal for one horizontal period; a first adder for adding an output signal of said operation circuit and an output signal of said delay circuit; a filter circuit for passing a specified frequency band of an output signal of said first adder; a first coefficient circuit for multiplying an output signal of said filter circuit with a specified coefficient; a second adder for adding the output signal of said operation circuit and an output signal of said coefficient circuit to use the sum output signal as an input signal to said delay circuit; a subtractor for subtracting the output signal of said delay circuit from the input signal of said delay circuit; an amplitude limiter for limiting the amplitude of an output signal of said subtractor; and a second coefficient circuit for multiplying an output of said amplitude limiter with a specified coefficient; an output signal of said second coefficient circuit being the another signal fed to said operation circuit, the output signal of said operation circuit being an output signal of said luminance signal processing circuit.
Claim 9
Dependent Claim
17 words
A luminance signal processing circuit according to claim 6, wherein said filter circuit possesses a high-emphasis characteristic.
Claim 10
Dependent Claim
17 words
A luminance signal processing circuit according to claim 6, wherein said filter circuit possesses a band-emphasis characteristic.
Claim 11
Dependent Claim
28 words
A luminance signal processing circuit according to claim 6, wherein said operation circuit is a subtractor, whereby said luminance signal processing circuit reduces noise in said input signal.
Claim 12
Dependent Claim
26 words
A luminance signal processing circuit according to claim 6, wherein said operation circuit is an adder, whereby said luminance signal processing circuit emphasizes said input signal.
Claim 13
Dependent Claim
128 words
A recursive comb filter comprising: a delay circuit for delaying a signal by one horizontal period; a first adder for adding an input signal and an output signal of said delay circuit; a filter circuit for passing a specified frequency band of an output signal of said first adder; a coefficient circuit for multiplying an output of said filter circuit with a specified coefficient; a second adder for adding said input signal and an output of said coefficient circuit to use the sum output signal as an input signal of said delay circuit; and a subtractor for subtracting the output signal of said delay circuit from the input signal of said delay circuit, an output signal of said subtractor being an output signal of said recursive comb filter.
Claim 14
Dependent Claim
128 words
A recursive comb filter comprising: a delay circuit for delaying a signal by one horizontal period; a first adder for adding an input signal and an output signal of said delay circuit; a filter circuit for passing a specified frequency band of an output signal of said first adder; a coefficient circuit for multiplying an output of said filter circuit with a specified coefficient; a second adder for adding said input signal and an output of said coefficient circuit to use the sum output signal as an input signal of said delay circuit; and a subtractor for subtracting the output signal of said delay circuit from the input signal of said delay circuit, an output signal of said subtractor being an output signal of said recursive comb filter.
Claim 15
Dependent Claim
16 words
A recursive comb filter according to claim 11, wherein said filter circuit possesses a high-emphasis characteristic.
Claim 16
Dependent Claim
16 words
A recursive comb filter according to claim 11, wherein said filter circuit possesses a band-emphasis characteristic.
References Cited (Backward Citations)
US4571613A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-31 | 1991-11-30 | 1992-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-31 | 1995-11-30 | 1996-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-31 | 1999-11-30 | 2000-05-31 | $7700.00 | Window Closed / Lapsed |