LCD panel CMOS display circuit

Claim 1

An LCD panel CMOS display circuit for line-scanning and controlling an LCD panel having a plurality of X and Y electrodes arranged in a matrix form and having a plurality of liquid crystal display cells between said X and Y electrodes, comprising: (a) a timing control circuit for generating a serial scanning data signal, a serial display data signal, a first shift clock signal, a second shift clock signal, a first control signal, and a second control signal; (b) a multi-power source for producing a first group of bias voltages and a second group of bias voltages; (c) a scanning data converter coupled to said timing control circuit for sequentially converting said scanning data from said timing control circuit in response to said first shift clock signal so as to convert said scanning data into scanning data in a parallel form which are output on a plurality of output lines; (d) a first gate having a plurality of output lines and coupled to said output lines of said scanning data converter for selectively transmitting said scanning data from said converter in response to said first control signal; (e) an X-bias selection circuit coupled to said first gate and including a plurality of first decoders and a plurality of drivers, each of said plurality of decoders coupled to one of said output lines of said first gate for converting a signal supplied thereto into a specific coded signal in response to a third control signal, each of said plurality of drivers coupled to a different one of said plurality of decoders for delivering a specific one of said first group of bias voltages to one of said X electrodes of said LCD matrix panel in response to its specific coded signal; (f) a display data holding circuit for converting said serial display data signal into parallel data in response to said second shift clock signal and for selectively outputting said parallel data on a plurality of output lines in response to said first shift clock signal; (g) a second gate having a plurality of output lines and coupled to said output lines of said display data holding circuit for selectively transmitting said parallel data in response to said first control signal; (h) a Y-bias selection circuit coupled to said second gate including a plurality of second decoders and a plurality of drivers, each of said plurality of decoders coupled to one of said output lines of said second gate for converting a signal supplied thereto into a specific coded signal in response to a fourth control signal, each of said plurality of drivers coupled to different one of said plurality of decoders for delivering a specific one of said second group of bias voltages to one of said Y electrodes of said LCD matrix panel in response to its specific coded signal; and (i) a mode switching circuit coupled to said first and second pluralities of decoders for transmitting said second control signal to said first and second pluralities of decoders when said first control signal is in a first logic level, whereby said LCD panel is placed in a display mode, and for ceasing the transmission of said second control signal when said first control signal is in a second logic level, whereby the same bias voltage is provided to said X and Y electrodes of said LCD panel so as to place said LCD panel in a non-display mode.