Differential phase shift keying demodulator

Claim 2

A differential phase shift keying demodulator comprising: (a) delay means for delaying a signal modulated by differential phase shift keying; (b) comparison means for comparing the output signal of said delay means and said modulated signal obtained without being delayed; and (c) sampling means for sampling the output signal of said comparison means a plurality of times for the period of delay effected by said delay means.

Claim 3

A demodulator according to claim 1, further comprising clock pulse generating means for generating a clock pulse signal.

Claim 4

A demodulator according to claim 2, wherein said sampling means is arranged to perform sampling by using said clock pulse signal.

Claim 5

A demodulator according to claim 3, wherein said delay means includes a shift register.

Claim 6

A demodulator according to claim 4, wherein said shift register is arranged to be driven by means of said clock pulse signal.

Claim 7

A demodulator according to claim 3, further comprising adjusting means for adjusting the timing of sampling by said sampling means according to the timing of data transmission by said modulated signal.

Claim 8

A demodulator according to claim 1, wherein the data transmission period per bit by said modulated signal is equal to the delay period of said delay means.

Claim 9

A demodulator according to claim 7, further comprising means for restoring to its original state a signal obtained by demodulating said modulated signal on the basis of the output of said sampling means produced within a period during which one bit of data is transmitted through said modulated signal.

Claim 10

A demodulator according to claim 8, wherein said comparison means includes an exclusive OR circuit which is arranged to receive the output signal of said delay means and said modulated signal.

Claim 11

A demodulator according to claim 8, wherein said sampling means includes an AND gate which is arranged to receive the output signal of said comparison means as a signal to be sampled.

Claim 12

A demodulator according to claim 10, wherein said restoring means includes detecting means which, for every period during which one bit of data is transmitted by said modulated signal, detects that the number of sampling signals produced from said AND gate reaches a predetermined number.

Claim 13

A demodulator according to claim 11, wherein said restoring means further includes means for sampling and holding the output signal of said detecting means produced within the period during which one bit of data is transmitted by said modulated signal.

Claim 14

A differential phase shift keying demodulator capable of demodulating signals of different kinds which are modulated by differential phase shift keying and have a varying transmission period per bit of data, comprising: (a) delay means for delaying a signal modulated by differential phase shift keying; (b) comparison means for comparing said signal delayed by said delay means with said modulated signal; and (c) setting means for setting a delay time of said delay means relative to the output of said comparison means at one of different lengths of time corresponding to the transmission period of said modulated signal per bit of data.

Claim 15

A differential phase shift keying demodulator capable of demodulating signals of different kinds which are modulated by differential phase shift keying and have a varying transmission period per bit of data, comprising: (a) delay means for delaying a signal modulated by differential phase shift keying; (b) comparison means for comparing said signal delayed by said delay means with said modulated signal; and (c) setting means for setting a delay time of said delay means relative to the output of said comparison means at one of different lengths of time corresponding to the transmission period of said modulated signal per bit of data.

Claim 16

A demodulator according to claim 13, wherein said delay means includes shift register means.

Claim 17

A demodulator according to claim 14, wherein said setting means includes change-over means for shifting the number of register stages of said shift register means relative to to the output of said comparison means from one number of stages to another.

Claim 18

A demodulator according to claim 15, wherein said shift register means includes series connected two shift registers; and said comparison means includes a first comparison circuit which compares the input signal of said series connected two shift registers with the output signal thereof and a second comparison circuit which compares the input signal of one of said two shift registers with the output signal thereof.

Claim 19

A demodulator according to claim 16, wherein said change-over means includes a switch circuit which is arranged to selectively produce, as the output signal of said comparison means, either the output signal of said first comparison circuit or the output signal of said second comparison circuit.

Claim 20

A demodulator according to claim 14, wherein said setting means includes frequency change-over means for shifting the frequency of a clock pulse signal to be used for driving said shift register means.