Wide range frequency synthesizer with reduced jitter

Claim 2

A frequency synthesizer for providing an output signal having a frequency different from that of a signal having a given frequency by a selected offset frequency, comprising a frequency control circuit, receiving said output signal or said signal having a given frequency as an input, for producing a reduced frequency pulse train having a frequency dependent on but less than the frequency of said one of said signals, said reduced frequency pulse train having jitter frequency components due to inequality in periods of time between successive pulses of the reduced frequency pulse train, an output circuit, receiving said reduced frequency pulse train, and having an output which is said output signal, and a jitter compensation circuit connected to said frequency control circuit for receiving a jitter-containing input therefrom, and providing an output connected to said output circuit for reducing jitter in the period of said output signal which would otherwise be caused as a result of said inequality, characterized in that said jitter compensation circuit comprises an analog integrator, and a d.c. removal circuit, for removing any d.c. voltage from a signal representative of the jitter, said analog integrator filtering said signal representative of the jitter, the synthesizer further includes a control device having at least one control signal output, said frequency control circuit comprises means responsive to said at least one control signal output for canceling extra cycles from, and adding extra cycles to, said input, for reducing the relative strength of any spurious signal in said output signal resulting from imperfect compensation by said jitter compensation circuit, and the synthesizer comprises a control signal compensation circuit connected to said control device, for compensating for jitter that would otherwise by caused by the control signal.

Claim 3

A synthesizer as claimed in claim 1, characterized in that said means responsive to said control signal output cancels extra cycles according to a first pulse sequence, and adds extra cycles according to a second pulse sequence, said first and second pulse sequences being interspersed.

Claim 4

A synthesizer as claimed in claim 2, characterized in that said first and second sequences together form a pseudo-random sequence.

Claim 5

A synthesizer as claimed in claim 1, comprising means for combining an output of said analog filter and an output of said control signal compensation circuit, to form a combined compensation signal.

Claim 6

A synthesizer as claimed in claim 4, characterized by comprising a detector arranged to detect any residual jitter remaining after application of said combined compensation signal, and a variable gain amplifier arranged for controlling the amplitude of said combined compensation signal, the gain of said amplifier being controlled by said detector to reduce said residual jitter.

Claim 7

A synthesizer as claimed in claim 1, characterized in that said frequency control circuit comprises a cycle cancellation circuit having an output and at least one input, said jitter-containing input being an input of said cycle cancellation circuit.

Claim 8

A synthesizer as claimed in claim 1, characterized in that said jitter-containing input is said reduced frequency pulse train.

Claim 9

A frequency synthesizer for providing an output signal having a frequency different from that of a signal having a given frequency by a selected offset frequency, comprising a pulse source for generating an offset pulse train having an average frequency equal to said selected offset frequency, a frequency control circuit, having an input, for producing a reduced frequency pulse train having a frequency less than said input, said frequency control circuit including a cycle cancellation circuit for canceling a cycle of said input for each pulse of said offset pulse train, an output circuit, receiving said reduced frequency pulse train, and having an output which is said output signal, and a jitter compensation circuit connected to said frequency control circuit and providing an output connected to said output circuit for reducing jitter in the period of said output signal which would otherwise be caused as a result of each cancelled cycle, characterized in that said output circuit comprises a variable frequency oscillator for generating said output signal, said output signal being said input to said frequency control circuit; and means for comparing said reduced frequency pulse train with said given signal, for varying the frequency of the variable frequency oscillator, said jitter compensation circuit comprises an analog integrator, and a d.c. removal circuit, for removing any d.c. voltage from a signal representative of the jitter resulting from cancellation of a cycle by said cycle cancellation circuit, said analog integrator filtering said signal representative of the jitter, and the synthesizer further includes a control device having at least one control signal output, and said frequency control circuit comprises means responsive to said at least one control signal output for canceling extra cycles from, and adding extra cycles to, said reduced frequency pulse train, for reducing the relative strength of any spurious signal in said output signal resulting from imperfect compensation by said jitter compensation circuit, and a control signal compensation circuit connected to said control device, for compensating for jitter that would otherwise be caused by the control signal.

Claim 10

A frequency synthesizer for providing an output signal having a frequency different from that of a signal having a given frequency by a selected offset frequency, comprising a pulse source for generating an offset pulse train having an average frequency equal to said selected offset frequency, a frequency control circuit, having an input, for producing a reduced frequency pulse train having a frequency less than said input, said frequency control circuit including a cycle cancellation circuit for canceling a cycle of said input for each pulse of said offset pulse train, an output circuit, receiving said reduced frequency pulse train, and having an output which is said output signal, and a jitter compensation circuit connected to said frequency control circuit and providing an output connected to said output circuit for reducing jitter in the period of said output signal which would otherwise be caused as a result of each cancelled cycle, characterized in that said output circuit comprises a variable frequency oscillator for generating said output signal, said output signal being said input to said frequency control circuit; and means for comparing said reduced frequency pulse train with said given signal, for varying the frequency of the variable frequency oscillator, said jitter compensation circuit comprises an analog integrator, and a d.c. removal circuit, for removing any d.c. voltage from a signal representative of the jitter resulting from cancellation of a cycle by said cycle cancellation circuit, said analog integrator filtering said signal representative of the jitter, and the synthesizer further includes a control device having at least one control signal output, and said frequency control circuit comprises means responsive to said at least one control signal output for canceling extra cycles from, and adding extra cycles to, said reduced frequency pulse train, for reducing the relative strength of any spurious signal in said output signal resulting from imperfect compensation by said jitter compensation circuit, and a control signal compensation circuit connected to said control device, for compensating for jitter that would otherwise be caused by the control signal.

Claim 11

A synthesizer as claimed in claim 8, characterized in that said cycle cancellation circuit forms part of said means responsive to said control signal output, and cancels said extra cycles; and said means responsive to said control signal output includes a pulse adder for adding pulses to the output of said cycle cancellation circuit.

Claim 12

A frequency synthesizer for providing an output signal having a frequency different from that of a given signal by a selected offset frequency, comprising means, including a reference frequency generator, for generating said given signal, a frequency control circuit, receiving said given signal as an input, for producing a reduced frequency pulse train having a frequency dependent on but less than the frequency of said given signal, said reduced frequency pulse train having jitter frequency components due to inequality in periods of time between successive pulses of the reduced frequency pulse train, an output circuit, receiving said reduced frequency pulse train, and having an output which is said output signal, and a jitter compensation circuit connected to said frequency control circuit and providing an output connected to said output circuit for reducing jitter in the period of said output signal which would otherwise be caused as a result of said inequality, characterized in that said jitter compensation circuit comprises an analog integrator, and a d.c. removal circuit, for removing any d.c. voltage from a signal representative of the jitter resulting from said inequality, said analog integrator filtering said signal representative of the jitter, and the synthesizer further includes a control device having at least one control signal output, and said frequency control circuit comprises means responsive to said at least one control signal output for canceling extra cycles from, and adding extra cycles to, said reduced frequency pulse train, for reducing the relative strength of any spurious signal in said output signal resulting from imperfect compensation by said jitter compensation circuit.

Claim 13

A frequency synthesizer for providing an output signal having a frequency different from that of a given signal by a selected offset frequency, comprising means, including a reference frequency generator, for generating said given signal, a frequency control circuit, receiving said given signal as an input, for producing a reduced frequency pulse train having a frequency dependent on but less than the frequency of said given signal, said reduced frequency pulse train having jitter frequency components due to inequality in periods of time between successive pulses of the reduced frequency pulse train, an output circuit, receiving said reduced frequency pulse train, and having an output which is said output signal, and a jitter compensation circuit connected to said frequency control circuit and providing an output connected to said output circuit for reducing jitter in the period of said output signal which would otherwise be caused as a result of said inequality, characterized in that said jitter compensation circuit comprises an analog integrator, and a d.c. removal circuit, for removing any d.c. voltage from a signal representative of the jitter resulting from said inequality, said analog integrator filtering said signal representative of the jitter, and the synthesizer further includes a control device having at least one control signal output, and said frequency control circuit comprises means responsive to said at least one control signal output for canceling extra cycles from, and adding extra cycles to, said reduced frequency pulse train, for reducing the relative strength of any spurious signal in said output signal resulting from imperfect compensation by said jitter compensation circuit.

Claim 14

A synthesizer as claimed in claim 10, characterized in that said frequency control circuit comprises a rate multiplier.

Claim 15

A synthesizer as claimed in claim 11, characterized by comprising a feedback control system including a detector, a low-pass filter, and a gain controlled amplifier, said detector being arranged to detect any residual jitter in said output signal, said low-pass filter receiving an output from said detector and providing a gain controlling signal to said gain-controlled amplifier, said amplifier amplifying a signal received from said analog integrator.

Claim 16

A synthesizer as claimed in claim 12, characterized by comprising a ramp generator having a reset input, and an output, and a comparator having the output of said ramp generator connected as one input, and having an output which is said output signal and is connected to said reset input of said ramp generator, said comparator having another input receiving a signal derived from said gain controlled amplifier output.

Claim 17

A synthesizer as claimed in claim 11, characterized in that said means responsive to said control signal output cancels extra signals from, and adds extra signals to, said given signal, to form an input received by said rate multiplier.

Claim 18

A synthesizer as claimed in claim 10, characterized in that said means responsive to said control signal output cancels extra signals from, and adds extra signals to, said given signal.