Pulse generating circuit

Claim 2

A pulse generating circuit for producing a pulse train consisting of a number of pulses each having a preselected pulse height, comprising: (a) a control node applied with a control signal; (b) an oscillation circuit operative to produce a raw pulse train consisting of a number of pulses including at least one pulse having a pulse height shorter than said preselected pulse height when said control signal appears at said control node and comprising (i) an amplification stage having a series combination of a first field-effect transistor, a first resistor and a second field-effect transistor coupled between a first source of voltage and a second source of voltage different in voltage level from the first source of voltage, said first field-effect transistor having a gate electrode coupled to said control node, (ii) a second resistor coupled between a drain node and a gate electrode of said second field-effect transistor, (iii) a crystal oscillator coupled between the drain node and the gate electrode of said second field-effect transistor, (ix) a first capacitor coupled between the gate electrode of said second field effect transistor and said second source of voltage, and (x) a second capacitor coupled between the drain node of said second field effect transistor and said second source of voltage, and; (c) an elimination circuit operative to eliminate said pulse with the pulse height shorter than said preselected pulse height from said raw pulse train and comprising (i) a pulse height monitoring circuit having a series combination of a third field-effect transistor, a third resistor and a fourth field-effect transistor coupled between said first source of voltage and said second source of voltage, said third and fourth field effect transistors having respective characteristics substantially identical with those of said first and second field-effect transistors, respectively, said third field-effect transistor having a gate electrode coupled to said control node and causing a dummy voltage level to appear at a drain node of said fourth field-effect transistor when said control signal appears at the control node, said fourth field-effect transistor having a gate electrode coupled to the drain node of said second field-effect transistor, (ii) a flip-flop circuit having two input nodes one of which is coupled to the drain node of the fourth field-effect transistor and the other of which is coupled to said control node and operative to produce an activating signal when said dummy voltage level excesses a preselected value, and (iii) a logic gate operative to produce said pulse train on the basis of said raw pulse train when said activating signal is supplied from said flip-flop circuit.

Claim 3

A pulse generating circuit as set forth in claim 1, in which said first and third field-effect transistors are of a p-channel type and said second and fourth field-effect transistors are of an n-channel type.

Claim 4

A pulse generating circuit as set fourth in claim 2, in which said first source of voltage is operative to provide a positive voltage level to said first and third field-effect transistors.

Claim 5

A pulse generating circuit as set forth in claim 2, in which said second source of voltage is operative to provide a ground voltage level to said second and fourth field-effect transistors.

Claim 6

A pulse generating circuit as set forth in claim 1, in which said logic gate performs an AND operation.

Claim 7

A pulse generating circuit as set forth in claim 1, in which said first resistor and said third resistor are different in resistance value from each other.

Claim 8

A pulse generating circuit producing a pulse train consisting of a number of pulses each having a preselected pulse height, comprising: (a) a control node applied with a control signal; (b) an oscillation circuit operative to produce a raw pulse train consisting of a number of pulses including at least one pulse having a pulse height shorter than said preselected pulse height when said control signal appears at said control node and comprising (i) an amplification stage having a series combination of a first field-effect transistor of a p-channel type, a first resistor and a second field-effect transistor of an n-channel type coupled between a first source of a positive voltage level and a second source of a ground voltage level, said first field-effect transistor having a gate electrode coupled to said control node, (ii) a second resistor coupled between a drain node and a gate electrode of said second field-effect transistor, (iii) a crystal oscillator coupled between the drain node and the gate electrode of said second field-effect transistor, (ix) a first capacitor coupled between the gate electrode of said second field effect transistor and said second source of the ground voltage level, and (x) a second capacitor coupled between the drain node of said second field effect transistor and said second source of the ground voltage level, and; (c) an elimination circuit operative to eliminate said pulse with the pulse height shorter than said preselected pulse height from said raw pulse train and comprising (i) a pulse height monitoring circuit having a series combination of a third field-effect transistor of the p-channel type, a third resistor and a fourth field-effect transistor of the n-channel type coupled between said first source of the positive voltage level and said second source of the ground voltage level, said third and fourth field effect transistors having respective characteristics substantially identical with those of said first and second field-effect transistors, respectively, said third field-effect transistor having a gate electrode coupled to said control node and causing a positive dummy voltage level to appear at a drain node of said fourth field-effect transistor when said control signal appears at the control node, said fourth field-effect transistor having a gate electrode coupled to the drain node of said second field-effect transistor, (ii) a flip-flop circuit having two input nodes one of which is coupled to the drain node of the fourth field-effect transistor and the other of which is coupled to said control node and operative to produce an activating signal when said dummy voltage level excesses a preselected value, and (iii) an AND gate operative to produce said pulse train on the basis of said raw pulse train when said activating signal is supplied from said flip-flop circuit.

Claim 9

A pulse generating circuit producing a pulse train consisting of a number of pulses each having a preselected pulse height, comprising: (a) a control node applied with a control signal; (b) an oscillation circuit operative to produce a raw pulse train consisting of a number of pulses including at least one pulse having a pulse height shorter than said preselected pulse height when said control signal appears at said control node and comprising (i) an amplification stage having a series combination of a first field-effect transistor of a p-channel type, a first resistor and a second field-effect transistor of an n-channel type coupled between a first source of a positive voltage level and a second source of a ground voltage level, said first field-effect transistor having a gate electrode coupled to said control node, (ii) a second resistor coupled between a drain node and a gate electrode of said second field-effect transistor, (iii) a crystal oscillator coupled between the drain node and the gate electrode of said second field-effect transistor, (ix) a first capacitor coupled between the gate electrode of said second field effect transistor and said second source of the ground voltage level, and (x) a second capacitor coupled between the drain node of said second field effect transistor and said second source of the ground voltage level, and; (c) an elimination circuit operative to eliminate said pulse with the pulse height shorter than said preselected pulse height from said raw pulse train and comprising (i) a pulse height monitoring circuit having a series combination of a third field-effect transistor of the p-channel type, a third resistor and a fourth field-effect transistor of the n-channel type coupled between said first source of the positive voltage level and said second source of the ground voltage level, said third and fourth field effect transistors having respective characteristics substantially identical with those of said first and second field-effect transistors, respectively, said third field-effect transistor having a gate electrode coupled to said control node and causing a positive dummy voltage level to appear at a drain node of said fourth field-effect transistor when said control signal appears at the control node, said fourth field-effect transistor having a gate electrode coupled to the drain node of said second field-effect transistor, (ii) a flip-flop circuit having two input nodes one of which is coupled to the drain node of the fourth field-effect transistor and the other of which is coupled to said control node and operative to produce an activating signal when said dummy voltage level excesses a preselected value, and (iii) an AND gate operative to produce said pulse train on the basis of said raw pulse train when said activating signal is supplied from said flip-flop circuit.

Claim 10

A pulse generating circuit producing a pulse train consisting of a number of pulses each having a preselected pulse height, comprising: (a) a control node applied with a control signal; (b) a resonant circuit operative to produce an oscillation signal; (c) a first inverter circuit operative to produce a raw pulse train at an output node thereof based on said oscillation signal in the presence of said control signal, said raw pulse train consisting of a number of pulses including at least one pulse having a pulse height shorter than the preselected pulse height; (d) a second inverter circuit coupled in series to said first inverter circuit and operative to produce a dummy voltage level at an output node thereof in the presence of said control signal; and (e) a logic circuit having a threshold voltage thereof and activated to produce said pulse train based on said raw pulse train when the dummy voltage level excesses the threshold voltage thereof, wherein said first inverter circuit is identical in circuit arrangement with said second inverter circuit.

Claim 11

A pulse generating circuit producing a pulse train consisting of a number of pulses each having a preselected pulse height, comprising: (a) a control node applied with a control signal; (b) a resonant circuit operative to produce an oscillation signal; (c) a first inverter circuit operative to produce a raw pulse train at an output node thereof based on said oscillation signal in the presence of said control signal, said raw pulse train consisting of a number of pulses including at least one pulse having a pulse height shorter than the preselected pulse height; (d) a second inverter circuit coupled in series to said first inverter circuit and operative to produce a dummy voltage level at an output node thereof in the presence of said control signal; and (e) a logic circuit having a threshold voltage thereof and activated to produce said pulse train based on said raw pulse train when the dummy voltage level excesses the threshold voltage thereof, wherein said first inverter circuit is identical in circuit arrangement with said second inverter circuit.

Claim 12

A pulse generating circuit as set forth in claim 8, in which said resonant circuit comprises a crystal oscillator having first and second electrodes, a first capacitor coupled between the first electrode of the crystal oscillator and a source of a ground voltage level, and a second capacitor coupled between the second electrode of the crystal oscillator and the source of the ground voltage level.

Claim 13

A pulse generating circuit as set forth in claim 8, in which said first inverter circuit comprises a series combination of a first field-effect transistor of a p-channel type, a first resistor and a second field-effect transistor of an n-channel type coupled between a first source of a positive voltage level and a second source of a ground voltage level, said first field-effect transistor having a gate electrode coupled to said control node, said second field-effect transistor having a gate electrode coupled to a drain node thereof through a second resistor.

Claim 14

A pulse generating circuit as set forth in claim 8, in which said second inverter circuit comprises a series combination of a third field-effect transistor of a p-channel type, a third resistor and a fourth field-effect transistor of an n-channel type coupled between a first source of a positive voltage level and a second source of a ground voltage level, said third field-effect transistor having a gate electrode coupled to said control node, said fourth field-effect transistor having a gate electrode coupled to the output node of said first inverter circuit.

Claim 15

A pulse generating circuit as set forth in claim 8, said logic circuit comprises a flip-flop circuit having a reset node coupled to said control node and a set node coupled to the output node of said second inverter circuit and operative to produce an activating signal when the dummy voltage level excesses a threshold voltage thereof, and an AND gate operative to produce said pulse train based on said raw pulse train in the presence of the activating signal.

Claim 16

A pulse generating circuit as set forth in claim 10, in which said second inverter circuit comprises a series combination of a third field-effect transistor of a p-channel type, a third resistor and a fourth field-effect transistor of an n-channel type coupled between a first source of a positive voltage level and a second source of a ground voltage level, said third field-effect transistor having a gate electrode coupled to said control node, said fourth field-effect transistor having a gate electrode coupled to the output node of said first inverter circuit, and in which one of said first and second field-effect transistors and the first resistor is different in characteristic from corresponding component of said series combination of said third field-effect transistor, said third resistor and said fourth field-effect transistor.