US4745296A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for optically testing circuit boards to detect incorrect circuit patterns
Assignee: Mania Elektronik Automatisation Entwicklung und Geraetebau GmbH
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Filing: 1986-11-12
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Granted: 1988-05-17
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Expires: 2006-11-12
Abstract
Abstract A circuit board having conductor tracks is optically tested for functionalaults by use of a computer controlled testing apparatus including at least one camera. The surface of the circuit board is scanned in a point-by-point manner by the camera to establish for each point scanned an image respresentative indicative of a conductor track area or a non-conductor track area. The surface of the circuit board is divided into a predetermined plurality of windows of predetermined size, and the image representations are associated with respective windows. For each window a determination is made of the sum of only the points of the window corresponding to a conductor track area or the sum of only the points of the window corresponding to a non-conductor track area. This establishes an identification value descriptive of the particular window. The identification values of the windows of the circuit board being tested are compared with predetermined values of corresponding respective windows of a reference master.
Inventors
- 👤 Hubert Driller
- 👤 Paul Mang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:51
CPC Classifications
G; G06; G06T; G06T7/00; G06T7/0002; G06T7/0004; G06T7/001; G06T2207/00; G06T2207/10; G06T2207/10056; G06T2207/30; G06T2207/30108; G06T2207/30141
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
189 words
In a process for optically testing a circuit board or the like having conductor tracks for functional faults, such as shorts, conductor track interruptions and conductor track misplacement, by means of a computer controlled testing apparatus including at least one camera, said process comprising scanning the surface of said circuit board in a point-by-point manner by means of said camera and thereby establishing for each point scanned an image representation indicative of a conductor track area or a non-conductor track area, and utilizing said representations to ascertain whether widths of said conductor tracks and spacings therebetween have required minimum values, the improvement comprising: dividing said surface of said circuit board into a predetermined plurality of windows of predetermined size; associating said image representations with respective said windows; counting for each said window only said points of said window corresponding to a conductor track area or said points of said window corresponding to a non-conductor track area, whereby the sum of such counting establishes an identification value descriptive of said window; and comparing said identification values of said windows with predetermined values of corresponding respective windows of a reference master.
Claim 2
Dependent Claim
189 words
In a process for optically testing a circuit board or the like having conductor tracks for functional faults, such as shorts, conductor track interruptions and conductor track misplacement, by means of a computer controlled testing apparatus including at least one camera, said process comprising scanning the surface of said circuit board in a point-by-point manner by means of said camera and thereby establishing for each point scanned an image representation indicative of a conductor track area or a non-conductor track area, and utilizing said representations to ascertain whether widths of said conductor tracks and spacings therebetween have required minimum values, the improvement comprising: dividing said surface of said circuit board into a predetermined plurality of windows of predetermined size; associating said image representations with respective said windows; counting for each said window only said points of said window corresponding to a conductor track area or said points of said window corresponding to a non-conductor track area, whereby the sum of such counting establishes an identification value descriptive of said window; and comparing said identification values of said windows with predetermined values of corresponding respective windows of a reference master.
Claim 3
Dependent Claim
56 words
The improvement claimed in claim 1, comprising for each said window, assigning black and white values to said scanned points indicative of conductor track areas and non-conductor track areas, respectively, and said counting comprises, for each said window, summing said black and white values to arrive at a relative gray value equal to said identification value.
Claim 4
Dependent Claim
76 words
The improvement claimed in claim 1, further comprising, for each said window, additionally determining coordinates of the center of gravity of said conductor track areas or of said non-conductor track areas by summing coordinates of said image representations indicative thereof, and thereby establishing an additional identification value descriptive of said window, and comparing said additional identification values of said windows with predetermined coordinate values of centers of gravity of corresponding respective windows of said reference master.
Claim 5
Dependent Claim
15 words
The improvement claimed in claim 1, wherein said reference master is a reference circuit board.
Claim 6
Dependent Claim
13 words
The improvement claimed in claim 1, wherein said reference master is a film.
Claim 7
Dependent Claim
116 words
The improvement claimed in claim 1, further comprising, for each window of said reference master, additionally determining a value representative of permissible variation in width of said conductor tracks due to manufacturing tolerances, said additionally determining comprising detecting which of said image representations are representative of points along a boundary line between a conductor track area and a non-conductor track area by comparing, for each said point, the image representation of said point with image representations of plural neighboring points in predetermined directions, and summing said boundary line points to result in said permissible width variation value, and comparing said permissible width variation value with corresponding values of respective windows of the circuit board being tested.
References Cited (Backward Citations)
US4559603A
Cited
US4635289A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-17 | 1991-11-16 | 1992-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-17 | 1995-11-16 | 1996-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-17 | 1999-11-16 | 2000-05-17 | $7700.00 | Window Closed / Lapsed |